Chapter 4. Continuous availability and manageability 101
Draft Document for Review September 2, 2008 5:05 pm4405ch04 Continuous availability and manageability.fm
Figure 4-6 Memory control hierarchy
Memory deconfiguration
Defective memory discovered at boot time is automatically switched off, unless it is already
the minimum amount required to boot. If the Service Processor detects a memory fault at
boot time, it marks the affected memory as bad so it is not to be used on subsequent reboots
(Memory Persistent Deallocation).
If the Service Processor identifies faulty memory in a server that includes CoD memory, the
POWER Hypervisor attempts to replace the faulty memory with available CoD memory. Faulty
resources are marked as deallocated and working resources are included in the active
memory space. Since these activities reduce the amount of CoD memory available for future
use, repair of the faulty memory should be scheduled as soon as is convenient.
Upon reboot, if not enough memory is available to meet minimum partition requirements the
POWER Hypervisor will reduce the capacity of one or more partitions. The HMC receives
notification of the failed component, triggering a service call.
4.2.2 Special uncorrectable error handling
While it is rare an uncorrectable data error can occur in memory or a cache. POWER6
processor-based systems attempt to limit, to the least possible disruption, the impact of an
uncorrectable error using a well-defined strategy that first considers the data source.
Sometimes, an uncorrectable error is temporary in nature and occurs in data that can be
recovered from another repository. For example:
Data in the instruction L1 cache is never modified within the cache itself. Therefore, an
uncorrectable error discovered in the cache is treated like an ordinary cache miss, and
correct data is loaded from the L2 cache.
The L3 cache of the POWER6 processor-based systems can hold an unmodified copy of
data in a portion of main memory. In this case, an uncorrectable error would simply trigger
a reload of a cache line from main memory.
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