3. TECHNICAL BRIEF
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Display Subsystem Overview
Figure 7-1. Display Subsystem Highlight
Note: For more information about connecting the LOCK, RECAL, and TVINT signals through the
GPIO2 and GPIO3 modules, see Chapter 25, GPIO.
The display subsystem includes the following main features:
• Display controller
– Display modes
• Programmable pixel display modes (1, 2, 4, 8, 12, 16, and 24 bits-per-pixel [BPP] modes)
• Programmable display size supported:
• XGA - 1024 x 768 VESA timings at 60 fps (pixel clock = 63.5 MHz)
SWPU176A–October 2009 Display Subsystem 1665
3.12.2.5 Display