EasyManuals Logo

LG LG-P970 Service Manual

LG LG-P970
295 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #75 background imageLoading...
Page #75 background image
3. TECHNICAL BRIEF
- 75 -
Copyright © 2011 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
PR
ELIMINA
RY
Device
L4 interconnect
Display subsystem
Remote
frame buffer
interface
Display
controller
cvideo2_out
cvideo2_vfb
TVINT
DSS_DATA[5:0]
dss_data
[0]/dsi_dx0
dss_data[1]/ dy0dsi_
dss_data[2]/ dx1dsi_
dss_data[3]/ dy1dsi_
dss_data[4]/ dx2dsi_
dss_data[5]/ dy2dsi_
IVA2.2
subsystem
interrupt
controller
L3 interconnect
MPU
subsystem
interrupt
controller
System DMA
controller
(sDMA)
PRCM
DSS1_ALWON_FCLK
DSS2_ALWON_FCLK
DSS_96M_FCLK
DSS_LINE_TRIGGER
DSS_IRQ
Functional clock1
Functional clock2
96-MHz clock
TV out
encoder
Digital data
24
4
DSS_L4_ICLK
GPIO2
L3 clock
DSS_L3_ICLK
DSS_TV_FCLK
54-MHz clock
System
control
module
Video DAC
stage
TVACEN
TVOUTBYPASS
vdda_dac
vssa_dac
Pin multiplexing
Pin multiplexing
DSI_DX0
DSI_DY0
DSI_DX1
DSI_DY1
DSI_DX2
DSI_DY2
DSI
complex I/O
DSI
protocol
engine
HS divider
Data
Controls
Status
PLL control
DSS_DMA_REQ[3:0]
DSI1_PLL_FCLK
DSI2_PLL_FCLK
vdds_dsi
vdd_dsi
DSI PLL
vss_dsi
cvideo1_out
Composite/Luma
Chroma
TV syncs
dss-001
DSI
PLL
controller
Syncs
DSS_PCLK
DSS_VSYNC
DSS_HSYNC
DSS_ACBIAS
dss_pclk
dss_vsync
dss_hsync
dss_acbias
dss_data[17:6]
dss_data[23:18]
L4 clock
DSS_DATA[17:6]
DSS_DATA[23:18]
cvideo1_vfb
cvideo1_rset
COMP_EN
TI Confidential NDA Restrictions
www.ti.com
Display Subsystem Overview
Figure 7-1. Display Subsystem Highlight
Note: For more information about connecting the LOCK, RECAL, and TVINT signals through the
GPIO2 and GPIO3 modules, see Chapter 25, GPIO.
The display subsystem includes the following main features:
Display controller
Display modes
Programmable pixel display modes (1, 2, 4, 8, 12, 16, and 24 bits-per-pixel [BPP] modes)
Programmable display size supported:
XGA - 1024 x 768 VESA timings at 60 fps (pixel clock = 63.5 MHz)
SWPU176AOctober 2009 Display Subsystem 1665
3.12.2.5 Display
The display subsystem provides the logic to display a video frame from the memory frame buffer on a liquid crystal
display panel or TV set.

Table of Contents

Other manuals for LG LG-P970

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the LG LG-P970 and is the answer not in the manual?

LG LG-P970 Specifications

General IconGeneral
BrandLG
ModelLG-P970
CategoryCell Phone
LanguageEnglish

Related product manuals