• Updated to include Orin Nano series modules in addition to Orin NX
series modules.
• Section 3.1. Added supported PCIe to NVMe configurations for
secondary boot storage.
• Table 6-1 and Section 6.1. Updated description of SYS_RESET*
behavior when driven by carrier board.
• Section 6.1. Added note that carrier boards must support VDD_IN at
5V (support for higher voltage on VDD_IN optional)
• Figure 6-4. Power Up Sequence with Power Button. Added missing
text for last line (carrier board supplies)
• Table 7-3. USB 3.2 and PCIe Lane Mapping: Corrected column title in
UPHY mapping table to Orin module instead of AGX Orin.
• Various: Updated on-module I2C pull-
• Table 2-1: Added mention of storage options on USB and PCIe
• Figure 2-1: Updated to include option for storage on USB 3.2 or PCIe
• Section 3.1:
> Corrected UPHY block to UPHY2 instead of UPHY1
> Added USB 3.2 option for storage
• Figure 5.1: Updated with Orin NX/Nano module
• Updated Table 6-1:
> Updated SLEEP/WAKE* to remove mention of pull-up on
module
> Updated SYS_RESET* on-module pull-up voltage
> Updated CLK_32K_OUT description
• Figure 6-3, Figure 6-4, Table 6-3, and Table 6-4: Updated
SYS_RESET_N delay from POWER_EN
• Figure 6-5: Updated figure to remove arrow from SHUTDOWN_REQ*
to carrier board supplies falling.
• Table 7-2:
> Corrected P/N swap for Orin signal names SF_PCIE7_CLK
(Pins 52/54)
> Corrected +/- swap for SF_PCIE9_CLK descriptions (Pins
227/229)
• Figure 9-1: Corrected P/N swap for SoC DPAUX pins
• Figure 9-2: Corrected P/N swap for SoC DPAUX and PIAUX221Z
device.
• Figure 9-8: Corrected P/N swap for SoC DPAUX
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