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Nvidia Jetson Orin NX Series User Manual
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DG
-
1093
1-001
_v1.1
|
Ap
ril 2
023
PRELI
MINAR
Y IN
FO
RMA
TION
SUB
JEC
T
T
O C
HA
NGE
Jetson Orin NX Series
and Jetson Orin
Nano
Series
Product Design Guide
2
Table of Contents
default chapter
5
Table of Contents
5
Chapter 1. Introduction
12
References
12
Attachments
13
Abbreviations and Definitions
13
Table 1-1. Abbreviations and Definitions
13
Chapter 2. Jetson Orin Module
15
Table 2-1. Jetson Orin Module Interfaces
15
Figure 2-1. Jetson Orin Module Block Diagram
16
Table 2-2. Jetson Orin Module Connector 260-Pin SO-DIMM Pinout Matrix
16
Chapter 3. Jetson Orin Module Boot Considerations
20
QSPI Boot
20
USB Recovery Mode
20
Chapter 4. Developer Kit Feature Considerations
22
Button Power MCU
22
USB Superspeed Hub
23
Power over Ethernet
23
TI TXB0108 Level Shifters
23
Features Not to be Implemented
23
Chapter 5. Modular Connector
24
Module Connector Details
24
Module to Mounting Hardware
24
Module Installation and Removal
25
Figure 5-1. Jetson Orin Module Installed in SODIMM Connector
25
Figure 5-2. Module to Connector Assembly Diagram
25
Chapter 6. Power
26
Table 6-1. Jetson Orin Module Power and System Pin Description
26
Power Supply and Sequencing
27
Figure 6-1. System Power and Control Block Diagram
29
Figure 6-2. System Power and Control Block Diagram
29
Figure 6-3. Power up Sequence no Power Button Auto Power on
30
Figure 6-4. Power up Sequence with Power Button
30
Figure 6-5. Power down Initiated by SHUTDOWN_REQ* Assertion
31
Figure 6-6. Power down Sudden Power Loss
31
Power Button Supervisor MCU Power-On
32
Table 6-2. Power Button Supervisor Control Signals
32
Figure 6-7. Power-On Button Circuit
33
Defined Behaviors
34
Power-Off -> Power-On (Power Button Case)
34
Figure 6-8. Power-Off to on Sequence Power Button Case
34
Table 6-3. Power-Off to on Timing Power Button Case
34
Power-Off -> Power-On (Auto-Power-On Case)
35
Power-On -> Power-Off (Long Power Button Press)
35
Figure 6-9. Power-Off to on Sequence Auto Power-On Case
35
Table 6-4. Power-Off to on Timing Auto Power-On Case
35
Figure 6-10. Power-On to off Power Button Held Low > 10 Seconds
36
Table 6-5. Power-On to off Timing Power Button Held Low > 10 Seconds
36
Chapter 7. USB and Pcie
37
Table 7-1. Jetson Orin Module USB 2.0 Pin Description
37
Table 7-2. Jetson Orin Module USB 3.2 and Pcie Pin Description
38
Table 7-3. UPHY0 Mapping Options (USB 3.2 and Pcie)
40
Table 7-4. UPHY2 Mapping Options (Pcie)
40
Usb
41
Figure 7-1. USB Micro B USB Device and Recovery Connection Example
41
Figure 7-2. USB 3.2 Type a Host Only Connection Example
41
USB 2.0 Routing Guidelines
42
USB 3.2 Routing Guidelines
42
Table 7-5. USB 2.0 Interface Signal Routing Requirements
42
Table 7-6. USB 3.2 Interface Signal Routing Requirements
42
Common USB Routing Guidelines
45
Figure 7-3. IL/NEXT Plot
45
Figure 7-4. TDR Plot
45
Table 7-7. Orin USB 2.0 Signal Connections
45
Table 7-8. Miscellaneous USB 2.0 Signal Connections
46
Table 7-9. Orin USB 3.2 Signal Connections
46
Pcie
47
Figure 7-5. Pcie Root Port Connections Example
47
Figure 7-6. Pcie Endpoint Connections Example
48
Pcie Routing Guidelines
49
Table 7-10. Pcie Interface Signal Routing Requirements up to Gen4
49
Figure 7-7. Insertion Loss S-Parameter Plot SDD21
51
Figure 7-8. Insertion Loss S-Parameter Plot SDD11
51
Table 7-11. Pcie Signal Connections
52
Chapter 8. Gigabit Ethernet
54
Figure 8-1. Orin Module Ethernet Connections
54
Table 8-1. Orin Module Gigabit Ethernet Pin Descriptions
54
Ethernet MDI Routing Guidelines
55
Figure 8-2. Gigabit Ethernet Magnetics and RJ45 Connections
55
Table 8-2. Ethernet MDI Interface Signal Routing Requirements
55
Table 8-3. Ethernet Signal Connections
55
Chapter 9. Display
56
Table 9-1. Orin Module Edp, DP, and HDMI Pin Descriptions
56
Edp and DP
57
Figure 9-1. DP and Edp Connection Example
57
Table 9-2. DP and HDMI Pin Mapping
57
Edp and DP Routing Guidelines
58
Figure 9-2. DP++ Connection Example
58
Figure 9-3. Edp and DP Differential Main Link Topology
58
Table 9-3. Edp and DP Main Link Signal Requirements Including DP_AUX
59
Figure 9-4. S-Parameter up to HBR2
61
Figure 9-5. S-Parameter up to HBR3
62
Table 9-4. Edp and DP Signal Connections
62
Hdmi
63
Figure 9-6. HDMI Connection Example
63
HDMI Routing Guidelines
64
Figure 9-7. HDMI CLK and Data Topology
64
Table 9-5. HDMI Interface Signal Routing Requirements
64
Figure 9-8. IL/FEXT Plot
68
Figure 9-9. TDR Plot
68
Table 9-6. HDMI Signal Connections
69
Chapter 10. MIPI CSI Video Input
70
Table 10-1. Orin Module CSI Pin Descriptions
70
Figure 10-1. CSI 2-Lane Connection Options
71
Table 10-2. Orin Module Camera Miscellaneous Pin Descriptions
71
Figure 10-2. CSI 4-Lane Connection Options
72
Figure 10-3. Available Camera Control Pins
72
CSI Routing Guidelines
73
Table 10-3. CSI Configurations
73
Table 10-4. MIPI CSI D-PHY Interface Signal Routing Requirements
73
Table 10-5. MIPI CSI Signal Connections
74
Table 10-6. Miscellaneous Camera Connections
74
Chapter 11. Audio
75
Table 11-1. Orin Module Audio Pin Descriptions
75
I2S Routing Guidelines
76
Figure 11-1. Audio Connection Example
76
Table 11-2. I2S Interface Signal Routing Requirements
76
Table 11-3. Audio Signal Connection
77
Chapter 12. Miscellaneous Interfaces
78
I2C
78
Table 12-1. Orin Module I2C Pin Descriptions
78
I2C Design Guidelines
79
I2C Routing Guidelines
79
Figure 12-1. I2C Connections
79
Table 12-2. I2C Interface Signal Routing Requirements
79
Spi
80
Table 12-3. I2C Signal Connections
80
Table 12-4. Orin Module SPI Pin Descriptions
80
SPI Routing Guidelines
81
Figure 12-2. SPI Connections
81
Figure 12-3. Basic SPI Initiator and Target Connections
81
Figure 12-4. SPI Topologies
81
Table 12-5. SPI Interface Signal Routing Requirements
81
Uart
82
Table 12-6. SPI Signal Connections
82
Table 12-7. Orin Module UART Pin Descriptions
82
Can
83
Figure 12-5. Orin Module UART Connections
83
Table 12-8. UART Signal Connections
83
Table 12-9. Orin Module CAN Pin Descriptions
83
CAN Routing Guidelines
84
Fan
84
Figure 12-6. Orin Module CAN Connections
84
Table 12-10. CAN Interface Signal Routing Requirements
84
Table 12-11. CAN Signal Connections
84
Debug
85
Figure 12-7. Orin Module Fan Connections
85
Table 12-12. Orin Module Fan Pin Descriptions
85
Table 12-13. Orin Module Debug UART Pin Descriptions
85
Table 12-14. Debug UART Connections
85
Figure 12-8. Debug UART Connections
86
Chapter 13. PADS
87
Internal Pull-Ups for Dual Voltage Block Pins Power at 1.8V
87
Schmitt Trigger Usage
87
Pins Pulled or Driven High During Power-On
88
Table 13-1. Pins Pulled or Driven High by Orin Prior to SYS_RESET* Inactive
88
Table 13-2. Pins with External Pull-Ups to Supply on before SYS_RESET* Inactive
88
Chapter 14. Unused Interface Terminations
89
Unused Multi-Purpose Standard CMOS Pad Interfaces
89
Unused Dedicated Special Purpose Pad Interfaces
89
Table 14-1. Unused MPIO Pins and Pin Group
89
Chapter 15. Design and Bring-Up Checklists
90
Chapter 16. Orin Module Pin Descriptions
91
Chapter 17. General Routing Guidelines
92
Signal Naming Convention
92
Table 17-1. Signal Type Codes
92
Routing Guidelines Format
93
Signal Routing Conventions
93
Routing Guidelines
93
General PCB Routing Guidelines
94
Figure 17-1. General PCB Routing Guidelines
94
Common High-Speed Interface Requirements
95
Figure 17-2. Common Mode Choke
95
Table 17-2. Common High-Speed Interface Requirements
95
Test Points for High-Speed Interfaces
96
Figure 17-3. Serpentine
96
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Nvidia Jetson Orin NX Series Specifications
General
Brand
Nvidia
Model
Jetson Orin NX Series
Category
Control Unit
Language
English
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