PRELIMINARY INFORMATION
Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 76
Chapter 13. PADS
Orin module signals that come from the SoC may glitch when the associated power rail is
enabled. This may affect pins that are used as GPIO outputs. Designers should take this into
account. GPIO outputs that must maintain a low state even while the power rail is being
ramped up may require special handling.
13.1 Internal Pull-Ups for Dual Voltage
Block Pins Power at 1.8V
Several of the MPIO pads are on blocks designed to be powered at either 1.8V or 3.3V. These
blocks are powered at 1.8V on Orin module, and the internal pull-up at initial Power-On is not
effective. The signal may only be pulled up a fraction of the 1.8V rail. Once the system boots,
software can configure the pins for 1.8V operation and the internal pull-ups will work
correctly. If these signals need the pull-ups during Power-On, external pull-up resistors
should be added. The following pins listed are the affected pins. These are the Orin module
pins on the dual voltage blocks powered at 1.8V with Power-On reset default of Internal pull-
up enabled.
SPI1_CS0*
SPI1_CS1*
13.2 Schmitt Trigger Usage
The MPIO pins have an option to enable or disable Schmitt-trigger mode on a per-pin basis.
This mode is recommended for pins used for edge-sensitive functions such as input clocks, or
other functions where each edge detected will affect the operation of a device. Schmitt-trigger
by the
Orin inputs. Input clocks include the I2S and SPI clocks (I2Sx_SCLK and SPIx_SCK) when Orin is
in target mode. The FAN_TACH pin [GPIO8] is another input that could be affected by noise on
the signal edges. Care should be taken if the Schmitt-trigger mode setting is changed from
the default initialization mode as this can influence interface timing.
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