Nvidia Jetson Orin NX Series User Manual

USB and PCIe
PRELIMINARY INFORMATION
Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 41
Table 7-11. PCIe Signal Connections
Module Pin
Name (Function)
Type
Termination
Description
PCIe Interface 0 (x4 Controller #4, Root Port or Endpoint)
PCIE0_TX3_N/P
PCIE0_TX2_N/P
PCIE0_TX1_N/P
PCIE0_TX0_N/P
DIFF OUT
Series 0.22uF
Capacitor
Differential Transmit Data Pairs: Connect to TX_N/P pins of PCIe
connector or RX_N/P pin of PCIe device through AC cap according
to supported configuration.
PCIE0_RX3_N/P
PCIE0_RX2_N/P
PCIE0_RX1_N/P
PCIE0_RX0_N/P
DIFF IN
Series 0.22uF
capacitors near Orin
Module pins or device if
device on main PCB.
Differential Receive Data Pairs: Connect to RX_N/P pins of PCIe
connector or TX_N/P pin of PCIe device through AC cap according
to supported configuration.
PCIE0_CLK_N/P
Root Port
Endpoint
DIFF OUT
DIFF IN
Differential Reference Clock Output: Connected to a mux on the
module that selects either SF_PCIE10_CLK or UPHY2_REFCLK2.
Connect to REFCLK_N/P pins of PCIe device/connector. For Root
Port operation, set the mux to select SF_PCIE10_CLK (GP21 = 0).
For Endpoint, set the mux to select UPHY2_REFCLK2 (GP21 = 1).
PCIE0_CLKREQ*
Root Port
Endpoint
I
O
-up to
VDD_3V3_SYS on
module
PCIe Clock Request for PCIE0_CLK: Connect to CLKREQ pins on
device or connectors. If the module is configured as an Endpoint,
include isolation between the clock request pin on the module and
the device/connector. One isolator should have the output to the
module and be powered by the 3.3V rail on the module. The other
isolator should have the output pointing at the connector or device
and be powered by the 3.3V rail at the connector or device. These
isolate the on-module pull-up resistors as well as ensures the
pins on both the Root Port and Endpoint sides will not be driven
high before the associated power is enabled.
PCIE0_RST*
Root Port
Endpoint
O
I
-up to
VDD_3V3_SYS on
module
PCIe Reset: Connect to PERST pins on device/connector(s). If the
module is configured as an Endpoint, include a isolator between
the reset pin on the module and the device/connector powered by
the 3.3V rail at the connector or device. The isolator should have
the output toward the module. This isolates the on-module pull-up
resistor as well as ensures this signal will not be pulled or driven
high before the module is powered on.
PCIe Interface 1 (x1 Controller #1, Root Port only)
PCIE1_TX0_N/P
DIFF OUT
Series 0.22uF
Capacitor
Differential Transmit Data Pair: Connect to TX_N/P pins of PCIe
connector or RX_N/P pin of PCIe device through AC cap according
to supported configuration.
PCIE1_RX0_N/P
DIFF IN
Series 0.22uF
capacitors near Orin
Module pins or device if
device on main PCB.
Differential Receive Data Pair: Connect to RX_N/P pins of PCIe
connector or TX_N/P pin of PCIe device through AC cap according
to supported configuration.
PCIE1_CLK_N/P
DIFF OUT
Differential Reference Clock Output: Connect to REFCLK_N/P
pins of PCIe device/connector
PCIE1_CLKREQ*
I/O
-up to
VDD_3V3_SYS on
module
PCIe Clock Request for PCIE1_CLK: Connect to CLKREQ pins on
device/connector(s)
PCIE1_RST*
O
-up to
VDD_3V3_SYS on
module
PCIe Reset: Connect to PERST pins on device/connector(s)
PCIe Interface 2 (x1 or x2 Controller #7. Root Port only)
CSI4_D3_N/P
(PCIE2_TX1_N/P)
CSI4_D0_N/P
(PCIE2_TX0_N/P)
DIFF OUT
Series 0.22uF
Capacitor
Differential Transmit Data Pair: Connect to TX_N/P pins of PCIe
connector or RX_N/P pin of PCIe device through AC cap according
to supported configuration.
CSI4_D1_N/P
(PCIE2_RX1_N/P)
CSI4_D2_N/P
(PCIE2_RX0_N/P)
DIFF IN
Series 0.22uF
capacitors near
module pins or device
if device on main PCB.
Differential Receive Data Pair: Connect to RX_N/P pins of PCIe
connector or TX_N/P pin of PCIe device through AC cap according
to supported configuration.

Nvidia Jetson Orin NX Series Specifications

General

Brand	Nvidia
Model	Jetson Orin NX Series
Category	Control Unit
Language	English