USB and PCIe
PRELIMINARY INFORMATION
Jetson Orin NX Series and Jetson Orin Nano Series DG-10931-001_v1.1 | 29
Orin SoC Pin Name
(See Note 4)
USB 3.2 Receive (Port #2)
USB 3.2
connector,
device or hub
USB 3.2 Transmit (Port #2)
Notes:
1. In the Direction column, Output is from Orin module. Input is to Orin module. Bidir is for Bidirectional signals.
2. The direction shown in this table for GPxxx_PCIEx_RST* and GP185_PCIE_WAKE* signals is true when used for those PCIe
functions. Otherwise, if used as GPIOs, the direction is bidirectional.
3. The light blue highlighting for some of the module pins/functions is just to highlight the different functionality on those pins.
4. The table above shows Module Pin Names and Orin SoC Pin Names. For the Orin Module Function, which can be very different
than the Module Pin name, see the Pinout Matrix, full Pin Desc. xls attached to this document, or Table 7-3 below.
The following tables shows the supported UPHY mapping for the UPHY blocks [2,0]. The
mapping tables indicate which lanes of each UPHY block can be assigned for USB or PCIe.
Only one of the supported configurations per UPHY block can be used in a design. Each UPHY
block is programmed independently. It is not required to select the same configuration on
both UPHY blocks.
Table 7-3. UPHY0 Mapping Options (USB 3.2 and PCIe)
Orin Module Configurations
PCIe x1 (C1), RP
Limited to Gen2
Table 7-4. UPHY2 Mapping Options (PCIe)
Orin Module Configurations
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