RCA 70/46 User Manual

TRANSLATION
MEMORY
(Cont'd)
Notes
READ-ONLY
MEMORY
PROGRAM
CONTROL AND
ARITHMETIC UNIT
Syste'Jn Structure
S = State Bit: indicates, when set, that the addressed page is non-
privileged. When
this bit is reset, it indicates that the addressed
page is privileged. When this bit is reset and the nonprivileged
bit in the ISR is set, a Paging Error Program Interrupt condition
occurs.
This bit is set and reset by the program.
E = Executable Bit: indicates, when set, that the page addressed in
memory by this translation word can be read as an operand or
instruction, but cannot be written into. If a program attempts to
write into a page with this bit set in the translation word, a
Paging Error Program Interrupt condition occurs. This bit
indicates, when reset, that the page addressed in memory can
be executed,
read or written into. This bit is set and reset by
the program.
M = Page Control Bit: indicates, when set, that a 2,048-byte page is
referenced. This
bit indicates, when reset, that a 4,096-byte page
is referenced.
If the high-order bit of the displacement field is
set and M is set, a Paging Error Program Interrupt condition
occurs. This
bit is set and reset by the program.
H = Page Address Bit: indicates, when set, and M is set, the high-order
address (2,048 bytes of a 4,096 byte page). This bit indicates,
when
reset and M is set, the low-order address (2,048 bytes of a
4,096 byte page). This bit is ignored if M is reset. This bit is set
and reset by the program.
XXX bits are for future expansion and must be zeros (program
restriction) .
• 1. The G condition is provided as a program flag to indicate written
into and/or accessed, respectively. A first time Read or Write to a
page would cause
the G bit to be set.
2. This translation memory is provided in addition to the 128-word
memory used
in scratch pad.
3. Addresses used in
I/O servicing and I/O data transfer are direct
and do not go through translation.
• Three banks of Read-Only Memory (ROM) are standard on the Model
70/46 Processor. Each ROM bank consists of 2,048 56-bit words (each
containing one micro-instruction of 53-bit [plus 3 parity bits] length).
In addition each ROM contains a 12-bit address register and a 54-bit
memory register.
The wired-in microprogranl logic contained in the first read-only
memory
bank controls the elementary operations when in the 70/45 or
70/46 Mode. The effective cycle time of the ROM banks is 480 nanoseconds
with a 56-bit access.
Although
the Read-Only Memory is a standard feature in the 70/46,
it is not accessible by programming and the programmer need not be
familiar with the detailed method of operation of the ROM.
•
The program control and arithmetic unit in the Model 70/46 Processor
interprets and executes the instructions stored in main memory. Registers
and indicators monitor the sequence of operations, perform automatic
accuracy checks, and communicate with the RCA standard interface in
the control of input/output devices.
6

RCA 70/46 Specifications

General

Brand	RCA
Model	70/46
Category	Computer Hardware
Language	English