MULTI-PROCESSOR
INSl
ALLA
liON
INTRODUCTION
OPERATIONAL
CHARACTERISTICS
• Installations where more
than
one computer shares peripheral equip-
ment
or
work loads require
extra
machine-program communications. To
enable
this
rapid
signaling between processors independent of
input/output
operations
the
Direct Control
feature
is provided.
To signal a receiving processor
(or
processors) a
Write
Direct instruc-
tion is used to effect
an
external
interrupt
in
the
receiving processor. To
enable the receiving processor to honor
this
external
interrupt
and
com-
plete
the
transfer,
a Read Direct instruction is used
(refer
to Privileged
Instructions section). This
Write
Direct action
of
one processor
to
another
is analogous to a Supervisor Call instruction
and
corresponding
interrupt
of
a user's
program
to
the
Interrupt
Control
State
(P
a
).
Some typical cases
for
which
this
feature
is used
are:
Request use
of
a control
file.
Notify
that
file
access
has
been completed.
Notify back-up system
that
a processor machine failure
has
been detected.
Notify- back-up system
that
a processor power failure
has
been detected.
Request assistance because
of
program
overload.
Request
for
task
assignments.
• The 8-bit
data
byte
transmitted
from
the
out
line
of
one processor to
the
in
line
of
a second processor in a multi-processor installation by means
of
the
Direct Control
feature
provides 256 code combinations. The code
sets can be
any
required by
the
program
including EBCDIC
and
USASCII
with
code
interpretation
being performed by
the
program.
When a
transmitting
processor issues a
Write
Direct instruction,
an
external
interrupt
is
set
in the receiving processor (specified by
the
I-Field
of
the
Write
Control instruction) in response
to
the signal. To service
the
interrupt,
the
receiving processor issues a Read Direct instruction to
accept
the
control byte
and
then
issues a
Write
Direct
with
an
acknowl-
edgement code
to
the
transmitting
processor.
(Write
Direct
of
an
acknowl-
edgement code does
not
require a
return
acknowledgement.) When
an
acknowledgement
has
been received
from
each
of
the
receiving processors
(if
more
than
one connected),
the
transmitting
processor
may
execute
another
transmission.
In
the event
of
power failing
in
a processor,
interrupt
occurs to proces-
sor
state
P
4.
In
a multi-processor installation
with
the
Direct Control
feature,
the
failing processor issues a
Write
Direct instruction
with
a
data
byte
of
all zero bits to all processors
it
is connected to
in
the
system.
Note: The Direct Control
feature
does not provide
error
checking on the
data
transmitted. When checking is required,
it
must
be performed
by program.
81
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