ADDRESSING
Paging
and
Segmentation
MEMORY
ADDRESS
TRANSLATION
• Locations in
main
memory
are
consecutively numbered
starting
with
zero.
In
forming
an
address,
the
base
address
(Bl B
2
)
and
the
index
(X
2
)
are
treated
as
unsigned 24-bit positive
binary
numbers.
The
displacement
(D
1
D
2
)
is
treated
as
a 12-bit positive
binary
number.
The
three
are
added
together
as
absolute
binary
numbers
and
overflow is ignored. The
results
of
these additions yields
an
18-bit effective address.
Any
address
that
is
within
the
effective address,
but
specifies
memory
not
available in
the
particular
installation, causes
an
interrupt
to occur.
Any
address
that
is outside
the
effective
address
as
shown above is
ignored. However, to
maintain
program
compatibility on all processors,
all
addressing
should assume a 24-bit effective address. Negative
indexing
may
be achieved
by
address
wrap-around
since overflow
bits
over
the
24-bit
address
are
ignored .
•
Paging
and
segmentation
are
used to allocate
more
memory space to
the
computer
program
than
is actually available
in
the
processor.
The
70/46 System uses special equipment
features
and
programming
to provide
this
virtual
memory capability.
The 70/46
main
memory is divided into blocks
of
equal size called
pages. A
70/46
program
can consist
of
many
of
these pages but,
during
any
one execution stage, only those pages
required
for
that
execution
stage
are
in
main
memory. The pages
that
are
not
required
are
maintained
in
subsidiary
storage. The
70/46
programming
relocates
program
pages
dynamically
within
main
memory so
that
programs
are
executable
in
different
main
memory locations.
The
70/46
basic
page
size is 4,096 bytes.
At
the
discretion
of
the
program,
a 2,048-byte
page
size
can
also be used.
This
shorter
page
length
makes
it
possible to pack
main
memory
more
tightly
as
well
as
reducing
the
transfer
time
between
subsidiary
storage
and
main
memory
for
short
routines
that
do
no
require
a full 4,096
byte
page
of
storage
space. Use
of
the
2,048 byte page, however, reduces
the
available
virtual
memory space by
half
since
the
addressing
scheme pro-
vides
for
only 512 pages regardless
of
whether
they
are
4,096
bytes
or
2,048 bytes.
The
70/46
provides a
grouping
of
the
virtual
memory
pages
into
segments. Segments
are
independent, logical entities composed
of
64 pages.
In
the
70/46
only
eight
of
the
32 potential
virtual
segments
are
imple-
mented, each segment consisting
of
64 pages.
If
all pages
of
all
eight
segments
are
4,096 byte pages, a total
virtual
memory
of
two million
bytes is available.
If
all pages
of
all segments
are
2,048
byte
pages, a
total
virtual
memory
of
one million bytes is available. Because
address
incre-
mentation
wraps
around
on 262,144 bytes (equivalent
of
a
segment),
no
equipment
means
are
provided to sequence a
program
from
one
segment
to another.
•
The
following two modes
are
defined
for
control
of
memory
address
translation:
1. 70/46 Mode: causes all
non-I/O
memory
addresses
(instruction
sequence
and
operands)
to be
translated
if
the
D-bit
within
each
address
is zero.
12
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