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RCA 70/46 User Manual
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MAXIMUM
MULTI·PROCESSOR
COMPLEX
OCT'
oCT2
PROCESSOR
oCT3
#1
oCT4
oCT5
oCTS
oCT1
oCT2
PROCESSOR
oCT3
#2
oCT4
oCT5
oCTS
oCTt
oCT2
PROCESSOR
oCT3
#3
oCT4
oCT5
oCTS
Multi-Processor
I
nB'tallation
•
The
following
illustration
demonstrates
the
manner
in
which
six
proces-
sors
may
be
interconnected
so
that
any
two
processors
may
communicate.
oCTl
oCT2
oCT3
PROCESSOR
oCT4
#4
oCT5
oCTS
oCT1
oCT2
oCT3
PROCESSOR
#5
oCT4
oCT5
oCTS
OCTl
oCT2
oCT3
PROCESSOR
oCT4
#S
oCT5
oCTS
Figure
14.
Maximum
Multi-Processor
Complex
85
93
95
Table of Contents
Table of Contents
3
RCA Model 70/46 Processor
10
Organization of Data
12
Data Formats
12
Numbering System
12
System Structure
13
Main Memory
13
Non-Addressable Main Memory
13
Scratch-Pad Memory
13
Translation Memory
14
Read-Only Memory
15
Program Control and Arithmetic Unit
15
Input/Output Control
17
Interval Timer
17
Instruction Formats
18
RS Format
18
SI Format
19
SS Format
19
Addressing
21
Program Interrupt
25
Introduction
25
Processor States
25
Processing State PI
25
Machine Condition State P 4
25
Processor State Registers
26
Program Counter
26
General Registers
27
Floating-Point Registers
27
Interrupt Status Registers
27
Interrupt Mask Registers
29
Program Mask Registers
29
Register Addressing
30
Interrupt Flag Register
30
Table of Contents
31
Interrupt Conditions
32
Interrupt Mechanization
32
Automatic Interrupt
32
Power Failure
33
External Signal no
33
Interval Timer
33
Elapsed Time Cluck 2 16 P a
33
Console Interrupt Request
34
Selector Channel no
33
Paging Error
34
Paging Queue
34
Supervisor Call Instruction 2 20 P a
34
Privileged Operation
35
Address Error
36
Data Error
36
Divide Error 2 26 P a
37
Exponent Overflow
37
Exponent Underflow** 2 28 P a
37
Decimal Overflow
37
Fixed Point Overflow
38
Test Mode
38
Program Controlled Interrupt
42
INPUT/OUTPUT Introduction
45
Selector Channels
45
Multiplexor Channel
46
Input/Output Operation
46
Assembly/Status Register
46
(Cont'D) Input/Output Initiation
47
Channel Servicing
47
Channel Address Word ( CAW)
49
Channel Block Address (CBA)
49
Channel Command Word (CCW)
49
Input/Output Channel Registers
54
Channel Address Register (CAR)
54
Channel Command Register-II (CCR-II)
54
Channel Command Register-I (CCR-I)
55
CBA Register
56
Input/Output Instructions
56
Start Device Instruction
58
Halt Device Instruction
61
Test Device Instruction
65
Check Channel Instruction
69
Input/Output Status Indicators
69
Condition Code
72
Channel Status Byte
73
Standard Device Byte
74
Sense Bytes
75
Channel Servicing
76
Servicing a Data Transfer
76
End and Chaining Servicing
81
Interrupt Servicing
86
MULTI-PROCESSOR INSTALLA Tlon
90
MULTI-PROCESSOR Introduction
90
Direct Control Interface
91
Static out Lines
91
Static in Lines
91
Signal out Line
91
External Signal in Line
91
Power Failure Line (PFND)
91
Power Failure Inhibit in Line (PFIR)
91
Dual Processor Complex
92
Master/Satellite Complex
93
Maximum Multi-Processor Complex
94
Operational Procedures
95
Transmission Procedure
95
Response Procedure
95
Interrupt Action
97
Privileged Instructions
97
Function Call (FC)
99
Special Function # 1 Load Translation Memory (LTM)
101
Special Function #2 Scan Translation Memory and Store (STMS)
103
Special Function # 3 Store Translation Memory (STM)
105
Fixed-Point Instructions
132
(Cont'D) Shift Left Single (SLA)
159
Shift Right Single (SRA)
160
Shift Left Double (SLDA)
161
Shift Right Double (SRDA)
162
Decimal Arithmetic Instructions
163
Instruction Format
164
Condiiion Code Utilization
165
Interrupt Action
165
Add Decimal (AP)
167
Subtract Decimal (SP)
168
Zero and Add (ZAP)
169
Compare Decimal (CP)
170
Multiply Decimal (MP)
171
Divide Decimal (DP)
172
Pack (PACK)
173
Unpack (UNPK)
174
Move with Offset (MVO)
175
Logical Instructions
176
Instruction Formats
177
Condition Code Utilization
178
Interrupt Action
178
Move (MVI) (MVC)
179
Move Numerics (MVN)
180
Move Zones (MVZ)
181
Test and Set (TS)
182
Compare Logical (CLR) (CL) (CLI) (CLC)
183
And (Nr) (N) (Ni) (Nc)
184
Or (Or) (0) (01) (Oc)
185
Exclusive or (XR) (X) (XI) (XC)
186
Test under Mask (TM)
187
Insert Character (IC)
188
Store Character (STC)
189
Load Address (LA)
190
Translate (TR)
191
Translate and Test (TRT)
192
Edit (ED)
193
Edit and Mark (EDMK)
196
Shift Left Single Logical (SLL)
198
Shift Right Single Logical (SRL)
199
Shift Left Double Logical (SLDL)
200
Shift Right Double Logical (SRDL)
201
Branching Instructions
202
Instruction Formats
202
Interrupt Action
203
Branch on Condition (BCR) (Be)
204
Branch and Link (BALR) (BAL)
205
Branch on Count (BCTR) (BCT)
206
Branch on Index High (BXH)
207
Branch on Index Low or Equal (BXLE)
208
Execute (EX)
209
Floa Ting-Point Instructions
210
Representation of Numbers
211
Normalization
211
Instruction Formats
211
Interrupt Action
213
Load (LER) (LE) (LDR) (LD)
214
Load and Test (LTER) (LTDR)
215
Load Complement (LCER) (LCDR)
216
Load Positive (LPER) (LPDR)
217
Load Negative (LNER) (LNDR)
218
Add Normalized (AER) (AE) (ADR) (AD)
219
Add Unnormalized (AUR) (AU) (AWR) (AW)
221
Subtract Normalized (SER) (SE) (SDR) (SD)
222
Subtract Unnormalized (SUR) (SU) (SWR) (SW)
223
Compare (CER) (CE) (CDR) (CD)
224
Halve (HER) (HDR)
225
Store (STE) (STD)
226
Multiply (MER) (ME) (MDR) (MD)
227
Divide (DER) (DE) (DDR) (DD)
228
Optional Features
229
Feature 5019-46 - Elapsed Time Clock
230
Feature 5003-46 - Direct Control
230
Feature 5040 Selector Channel
230
Feature 5041- Selector Channel
230
Feature 5042 Selector Channel
230
Appendices
232
B - Program Interrupts
246
C - Input/Output Service Request
248
Extended Binary-Coded-Decimal Interchange Code
249
E - USA Standard Code for Information Interchange
250
Character Codes
251
Powers of Two Table
254
H - Hexadecimal-Decimal Number Conversion
257
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RCA 70/46 Specifications
General
Brand
RCA
Model
70/46
Category
Computer Hardware
Language
English
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