SARA-R4/N4 series - System Integration Manual
UBX-16029218 - R11 Design-in Page 51 of 157
2 Design-in
2.1 Overview
For an optimal integration of the SARA-R4/N4 series modules in the final application board, follow the
design guidelines stated in this section.
Every application circuit must be suitably designed to guarantee the correct functionality of the relative
interface, but a number of points require particular attention during the design of the application device.
The following list provides a rank of importance in the application design, starting from the highest
relevance:
1. Module antenna connection: ANT and ANT_DET pins.
Antenna circuit directly affects the RF compliance of the device integrating a SARA-R4/N4 series module
with applicable certification schemes. Follow the suggestions provided in the relative section 2.4 for the
schematic and layout design.
2. Module supply: VCC and GND pins.
The supply circuit affects the RF compliance of the device integrating a SARA-R4/N4 series module with
the applicable required certification schemes as well as the antenna circuit design. Very carefully follow
the suggestions provided in the relative section 2.2.1 for the schematic and layout design.
3. USB interface: USB_D+, USB_D- and VUSB_DET pins.
Accurate design is required to guarantee USB 2.0 high-speed interface functionality. Carefully follow the
suggestions provided in the relative section 2.6.2 for the schematic and layout design.
4. SIM interface: VSIM, SIM_CLK, SIM_IO, SIM_RST pins.
Accurate design is required to guarantee SIM card functionality reducing the risk of RF coupling.
Carefully follow the suggestions provided in relative section 2.5 for schematic and layout design.
5. System functions: RESET_N and PWR_ON pins.
Accurate design is required to guarantee that the voltage level is well defined during operation. Carefully
follow the suggestions provided in relative section 2.3 for schematic and layout design.
6. Other digital interfaces: UART, SPI, SDIO, I
2
C, I
2
S, GPIOs and reserved pins.
Accurate design is required to guarantee correct functionality and reduce the risk of digital data
frequency harmonics coupling. Follow the suggestions provided in sections 2.6.1, 2.6.2, 2.6.3, 2.6.4, 2.6.5,
2.7, 2.8 and 2.9 for the schematic and layout design.
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