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LogiCORE IP Spartan-6
Xilinx LogiCORE IP Spartan-6 User Manual
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LogiCORE™ IP Spar
tan
®
-6
FPGA GTP T
ransceiver
Wizar
d v1.8
Getting Star
ted Guide
UG546 (v1.8) De
cember 14, 2010
2
Table of Contents
Default Chapter
2
Revision History
2
Table of Contents
3
Preface: about this Guide
5
Guide Contents
5
Additional Resources
5
Conventions
5
Typographical
6
Online Document
7
Chapter 1: Introduction
9
About the Wizard
9
Recommended Design Experience
10
Related Xilinx Documents
10
Additional Wizard Resources
10
Technical Support
10
Feedback
10
Spartan-6 FPGA GTP Transceiver Wizard
10
Document
11
Chapter 2 : Installation and Licensing
13
System Requirements
13
Before You Begin
13
Installing the Wizard
14
Verifying Your Installation
14
Chapter 3: Running the Wizard
15
Overview
15
Setting up the Project
16
Creating a Directory
16
Setting the Project Options
17
Generating the Core
18
GTP Placement and Clocking
19
Line Rate and Protocol Template
21
10B Optional Ports
24
Synchronization and Clocking
25
RX Comma Alignment
27
Preemphasis, Termination, and Equalization
29
RX OOB, PRBS, and Loss of Sync
31
RX PCI Express, SATA Features
33
Channel Bonding, Clock Correction
36
Clock Correction Sequence
39
Summary
40
Chapter 4: Quick Start Example Design
41
Overview
41
Implementing the Example Design
41
Functional Simulation of the Example Design
42
Using Modelsim
42
Using the ISE Simulator
43
Using Chipscope Pro Cores with the Spartan-6 FPGA GTP Transceiver Wizard Core
43
Chapter 5: Detailed Example Design
45
Directory and File Structure
45
Directory and File Contents
46
Project Directory
46
Project Directory>/<Component Name
46
Component Name>/Doc
47
Component Name>/Example Design
47
Component Name>/Implement
48
Implement/Results
48
Component Name>/Simulation
49
Simulation/Functional
49
Example Design
50
Example Design Hierarchy
51
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Xilinx LogiCORE IP Spartan-6 Specifications
General
Brand
Xilinx
Model
LogiCORE IP Spartan-6
Category
Transceiver
Language
English
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