Xilinx LogiCORE IP Spartan-6 User Manual

42 www.xilinx.com Spartan-6 FPGA GTP Transceiver Wizard v1.8
UG546 (v1.8) December 14, 2010
Chapter 4: Quick Start Example Design
Functional Simulation of the Example Design
Using ModelSim
The Spartan-6 FPGA GTP Transceiver Wizard provides a quick way to simulate and
observe the behavior of the wrapper using the provided example design and script files.
Prior to simulating the wrapper with ModelSim, the functional (gate-level) simulation
models must be generated. All source files in the following directories must be compiled to
a single library as shown in
Table 4-1. See the Synthesis and Simulation Design Guide for
ISE
®
12.4, available in the ISE
®
Software Documentation for instructions on how to
compile ISE simulation libraries.
The Wizard provides a command line script for use within ModelSim. To run a VHDL or
Verilog ModelSim simulation of the wrapper, use the following instructions:
1. Launch the Modelsim simulator and set the current directory to
<project_directory>/<component_name>/simulation/functional
2. Set the MTI_LIBS variable:
modelsim> setenv MTI_LIBS <path to compiled libraries>
3. Launch the simulation script:
modelsim> do simulate_mti.do
The ModelSim script compiles the example design and test bench, and adds the relevant
signals to the wave window.
Table 4-1: Required ModelSim Simulation Libraries
HDL Library Source Directories
Verilog UNISIMS_VER
< Xilinx dir >/spartan6/verilog/src/unisims
< Xilinx dir >/spartan6/secureip/mti
VHDL UNISIM
< Xilinx dir >/spartan6/vhdl/src/unisims/primitive
< Xilinx dir >/spartan6/secureip/mti

Xilinx LogiCORE IP Spartan-6 Specifications

General

Brand	Xilinx
Model	LogiCORE IP Spartan-6
Category	Transceiver
Language	English