Xilinx LogiCORE IP Spartan-6 User Manual

Spartan-6 FPGA GTP Transceiver Wizard v1.8 www.xilinx.com 25
UG546 (v1.8) December 14, 2010
Generating the Core
Synchronization and Clocking
The Synchronization and Clocking screen (page 4) of the Wizard (Figure 3-8) provides
settings for latency, buffering, and clocking of the transmitter and receiver. The RX comma
alignment settings are also provided.
Table 3-7 lists the source signal options and Table 3-9
lists the optional ports.
The Enable TX buffer setting controls whether the TX buffer is enabled or bypassed. See
the Spartan-6 FPGA GTP Transceivers User Guide for details on this setting.
The PCI EXPRESS example uses the TX buffer.
The Enable RX buffer setting controls whether the RX buffer is enabled or bypassed. If the
RX buffer is deselected, then the RX Phase Alignment circuit is enabled.
The PCI EXPRESS example does not use the RX Phase Alignment circuit.
X-Ref Target - Figure 3-8
Figure 3-8: Synchronization and Clocking - Page 4

Xilinx LogiCORE IP Spartan-6 Specifications

General

Brand	Xilinx
Model	LogiCORE IP Spartan-6
Category	Transceiver
Language	English