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Xilinx ML605 User Manual
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ML605 Hardware User Guide
www
.xilinx.com
43
UG534
(v1.2.1) January 21, 2010
Detailed Des
cription
X-Ref Target - Figure 1-14
Figure 1-
14:
IIC Bus T
opolog
y
U1
J6
3
P
3
U
3
8
BANK
3
4
IIC_
S
D
A_MAIN_L
S
IIC_
S
CL_MAIN_L
S
IIC_
S
DA
_
S
FP
IIC_
S
CL_
S
FP
IIC_
S
DA
_
DVI
IIC_
S
CL_D
VI
FMC_LPC_IIC_
S
DA
_
L
S
FMC_LPC_IIC_
S
CL_L
S
FMC_LPC_IIC_
S
CL
U6
J64
J1
FMC_LPC_IIC_
S
DA
IIC_CLK_D
VI_F
IIC_
S
CL_MAIN
S
T MICRO
M24C08-WD
W6TP
FMC HPC
COLUMN C
2 K
b
EEPROM on
a
ny FMC LPC
Mezz
a
nine C
a
rd
DDR
3
S
ODIMM
S
OCKET
P4
S
FP MODULE
CONNECT
OR
IIC_
S
D
A_MAIN
S
FP_MOD_DEF2
S
FP_MOD_DEF1
IIC_
S
D
A_D
VI_F
BANK 1
3
BANK
3
4
BANK
33
FPGA IIC
INTERF
ACE
FMC LPC
COLUMN C
2 K
b
EEPROM on
a
ny FMC LPC
Mezz
a
nine C
a
rd
Addr:
0b1010001
Addr:
0b1010000
Addr:
0b1110110
Addr:
0b1010100
thro
u
gh
0b1010111
Addr:
0b1010000
Addr:
0b1010000
Addr:
0b1010011
2 K
b
EEPROM
Addr:
0b0011011
T
emper
a
t
u
re
S
en
s
or
D
VI CONN
D
VI CODEC
CHRONTEL
CH7
3
0C-TF
LEVEL
S
HIFTER
UG5
3
4_14_092109
LEVEL
S
HIFTER
LEVEL
S
HIFTER
LEVEL
S
HIFTER
42
44
Table of Contents
Default Chapter
2
Revision History
2
Table of Contents
3
Preface: about this Guide
5
Guide Contents
5
Additional Documentation
5
Additional Support Resources
6
Chapter 1: ML605 Evaluation Board
7
Overview
7
Additional Information
7
Features
8
Block Diagram
10
Related Xilinx Documents
10
Detailed Description
11
1 Virtex-6 XC6VLX240T-1FFG1156 FPGA
13
Configuration
13
I/O Voltage Rails
14
2 MB DDR3 Memory SODIMM
15
3 Mb Platform Flash XL
20
4 MB Linear BPI Flash
20
ML605 Flash Boot Options
21
5 System ACE CF and Compactflash Connector
24
6 Usb Jtag
26
7 Clock Generation
27
Oscillator (Differential)
27
Oscillator Socket (Single-Ended, 2.5V)
27
SMA Connectors (Differential)
29
8 Multi-Gigabit Transceivers (GTX Mgts)
31
9 PCI Express Endpoint Connectivity
32
10 SFP Module Connector
35
100 /1000 Tri-Speed Ethernet PHY
36
SGMII GTX Transceiver Clock Generation
37
12 USB-To-UART Bridge
39
13 USB Controller
40
506 DVI Codec
41
15 IIC Bus
42
Kb NV Memory
44
16 Status Leds
45
Ethernet PHY Status Leds
46
FPGA INIT and DONE Leds
47
17 User I/O
47
User Leds
48
User Pushbutton Switches
49
User DIP Switch
50
User SMA GPIO
51
LCD Display (16 Character X 2 Lines)
52
18 Switches
53
Power On/Off Slide Switch SW2
53
FPGA_PROG_B Pushbutton SW4 (Active-Low)
54
SYSACE_RESET_B Pushbutton SW3 (Active-Low)
54
System ACE CF Compactflash Image Select DIP Switch S1
55
Mode, Osc Enable, Boot EEPROM Select, and Addr Select DIP Switch S2
56
19 VITA 57.1 FMC HPC Connector
57
20 VITA 57.1 FMC LPC Connector
63
21 Power Management
65
AC Adapter and Input Power Jack/Switch
65
Onboard Power Regulation
66
22 System Monitor
68
Configuration Options
73
Connector Pinout
77
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Xilinx ML605 Specifications
General
Brand
Xilinx
Model
ML605
Category
Motherboard
Language
English
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