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Zynq UltraScale+ User Manual

Zynq UltraScale+
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RFSoC Data Converter Evaluation Tool User Guide 13
UG1287 (v2018.2) October 1, 2018 www.xilinx.com
Chapter 2
Package Details
The evaluation tool ZIP file package
rdf0476-zcu111-rf-dc-eval-tool-2018-2.zip
contains the following components grouped by application processor unit (APU) or
programmable logic (PL).
APU
petalinux_bsp: PetaLinux board support package (BSP) is included to build a
pre-configured SMP Linux image for the APU. The BSP includes the following components:
First stage boot loader (FSBL)
ARM trusted firmware (ATF)
•U-Boot
Linux kernel
Device tree
Root file system (rootfs)
PL
Vivado: Vivado IP integrator design that integrates the RF Data Converter subsystem, AXI
DMA, Stream Pipe, AXI Interconnect, and PL DDR controller.
Host System GUI
The user interface connecting to the ZCU111 platform via Ethernet cable.
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Zynq UltraScale+ Specifications

General IconGeneral
BrandZynq
ModelUltraScale+
CategoryMedia Converter
LanguageEnglish