Zynq UltraScale+ User Manual

RFSoC Data Converter Evaluation Tool User Guide 21
UG1287 (v2018.2) October 1, 2018 www.xilinx.com
Chapter 3: Hardware Design
ADC Data Flow
Figure 3-8 shows the datapath implementation for 8-channel RF-ADC (RF-ADC0 and
RF-ADC7). The default configuration of Real to IQ is enabled in the design so that all
possible streaming interfaces from RF-ADC are accessible.
All the incoming ADC streams are gated through the control switch logic. After the gates
are enabled, the I and Q streams are fed through IQ Merge logic. Based on user selection,
either a real or a complex stream is passed on to the AXIS FIFO. The Channel Select MUX
connects one of the AXIS FIFO to DMA, based on user selection. This data is further
provided to SG DMA to be stored in PL DDR memory. The synchronization among all eight
channels is achieved through control switch logic. A common global start signal is used for
this purpose.
X-Ref Target - Figure 3-8
Figure 3-8: Datapath Implementation for 8 Channel RF-ADC
PL DDR +
MIG
SG DMA
Channel
Select Mux
ADC0
Control
Switch
I & Q Merge
AXIS FIFO
64 KS
ADC1
Control
Switch
I & Q Merge
AXIS FIFO
64 KS
ADC2
Control
Switch
I & Q Merge
AXIS FIFO
64 KS
ADC3
Control
Switch
I & Q Merge
AXIS FIFO
64 KS
ADC4
Control
Switch
I & Q Merge
AXIS FIFO
64 KS
ADC5
Control
Switch
I & Q Merge
AXIS FIFO
64 KS
ADC6
Control
Switch
I & Q Merge
AXIS FIFO
64 KS
ADC7
Control
Switch
I & Q Merge
AXIS FIFO
64 KS
128 bits x 512 MHz 256 bits x 512 MHz
256 bits x 300 MHz
X21302-092518
Send Feedback

Zynq UltraScale+ Specifications

General

Brand	Zynq
Model	UltraScale+
Category	Media Converter
Language	English