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Zynq UltraScale+ User Manual

Zynq UltraScale+
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RFSoC Data Converter Evaluation Tool User Guide 2
UG1287 (v2018.2) October 1, 2018 www.xilinx.com
Revision History
The following table shows the revision history for this document.
Section Revision Summary
10/01/2018 Version 2018.2
DAC Data Flow Added information about feeding data to the RF-DAC.
Streaming MUX Added channel control selection information.
GPIO Selection Replaced Table 3-2.
Application Flow Added DDR and BRAM selection information and
information to start DMA.
DAC Flow for PL DDR Added this section.
Example Commands and Responses Added commands to Table A-1.
08/14/2018 Version 2018.2
Initial Xilinx release N/A
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Zynq UltraScale+ Specifications

General IconGeneral
Max TransceiversUp to 32
Transceiver SpeedUp to 32.75 Gbps
FamilyZynq UltraScale+
Processor CoresQuad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
Max MemoryDDR4
Power ConsumptionVaries by configuration, typically 10W to 30W
Operating TemperatureIndustrial (-40°C to +100°C), Extended (-40°C to +125°C)
Package OptionsVarious BGA packages
CategoryFPGA SoC