RFSoC Data Converter Evaluation Tool User Guide 28
UG1287 (v2018.2) October 1, 2018 www.xilinx.com
Chapter 4: Clocking
First, the PL SysRef is synchronized to the incoming PL clock for both DAC and ADC as
shown in Figure 4-2. This output of the second stage synchronizer is connected to
user_sysref ports of RFDC IP.
Refer to Zynq UltraScale+ RFSoC RF Data Converter LogiCORE IP
Product Guide (PG269)
for more details on multi-tile synchronization [Ref 9].
Clock Switching
The design supports multi-tile synchronization (MTS) mode and non-MTS mode. The
requirements for both modes are different. In MTS mode, all the DAC and ADC streams
should be triggered and captured at the same time. Hence all the DAC fabric paths
associated with different tiles are sourced by a common PL clock. This is the same case with
all the ADC paths. In non-MTS mode, the streaming interface clocks can be sourced by their
respective DAC and ADC tile clocks. The switching of the clock is controlled via a clock MUX
primitive BUFGMUX (see Figure 4-3 and Figure 4-4). Clock selection depends on whether
MTS mode is selected or not.
The other requirement of MTS mode is that all the incoming and outgoing streams of RFDC
IP should be triggered at the same instant. This is achieved using a combination of control
switch and channel control logic (Figure 4-5 and Figure 4-6). Figure 4-6 shows the channel
control scheme implemented in the design. The individual channel control signal is
generated using PS-GPIO pins. Later on, these signals are synchronized with respect to the
selected clock from BUFGMUX. This signal acts as an individual channel start/stop signal
which is fed to the control switch block of the ADC/DAC datapath. However, in MTS mode,
X-Ref Target - Figure 4-3
Figure 4-3: Clock MUX Selection
Multi-Tile Mode
BUFGMUX
Tile Clock
PL Fabric Clock
X21246-091318
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