ConnectCore for i.MX51
©2011DigiInternational,Inc. 44
– J2.115 - SPI1_SCLK (used on the module as communication channel with Freescale
PMIC)
– J2.88 - SD2_CMD (used on the module as communication channel for Wireless LAN
interface, if present)
The I
2
C interface provides the following capabilities:
Compatibility with I
2
C bus standard
Multiple-master operation
Software programmable for one of 64 different serial clock frequencies
Software selectable acknowledge bit
Start and stop signal generation detection
Repeated START signal generation
Acknowledge bit generation/detection
Bus-busy detection
Video Subsystem
The i.MX51 processor has a video subsystem that includes the following modules:
Video Processing Unit (VPU): a multi-standard video encoder/decoder
Image Processing Unit (IPU): providing connectivity to displays, related processing,
synchronization and control
TV encoder (TVE) bride: providing optional translation from the digital display
interface supported by the IPU to SDTV analog and some HDTV interfaces
Video Processing Unit (VPU)
The video processing unit of the i.MX51 is a high performance, multistandard video
processing unit that can perform H.264 BP/MP/HP, VC-1 SP/MP/AP, MPEG4 SP/ASP, Divx, RV8/
9, and MPEG2 MP decoding up to 1920 × 1088 resolution. It supports multiple video codecs
simultaneously.
The detailed features of the VPU are as follows:
Multi-standard video codec
– H.264/AVC decoder for baseline profile, main profile and high profile
– VC-1 decoder for simple profile, main profile and advanced profile
– MPEG-4 decoder for simple profile, advanced simple profile except GMC
– H.263 decoder for baseline profile
– Divx Home Theater decoder for profile (version 3.x, 4.x, 5.x, 6.x) and Xvid
– MPEG-2 decoder for main profile @ high level
– RV decoder for profile 8/9/10
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