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6 IEEE 488.2 Register model
6.1 Introduction to IEEE 488.2
The topics discussed in sections 4.2 to 4.3 are for the most part transparent to
the user during normal operation of the matrix. These sections are here mainly
for informational purpose. These sections describe a minimal register model
that is required to be able to perform a safe handshaking between the controller
and the matrix. In the matrix a status system records various conditions and
states in 2 registers. Each of the register groups is made up of several low-
level registers called Condition Registers, Event Registers, and Enable
Registers.
6.2 Condition Register
A condition register continuously monitors the state of the instrument. The bits
in the condition register are updated in real time and the bits are not latched or
buffered. This is a read-only register and bits are not cleared when you read
the register. A query of a condition register returns a decimal value which
corresponds to the binary-weighted sum of all bit set in that register.
6.3 Event Register
An event register latches the various events from the condition register. There
is no buffering in this register; while an event bit is set, subsequent events
corresponding to that bit are ignored. This is a read-only register. Once a bit is
set, it remains set until cleared by a query command (such as *CLS). A query
of this register returns a decimal value that corresponds to the binary-weighted
sum of all bits in that register.
6.4 Enable Register
An enable register defines which bits in the event register will be reported to the
Status Byte resister group. You can write to or read from an enable register. A
*CLS command will not clear the enable register but it does clear all bits in the
event resister. To enable bit in the enable register to be reported to the Statue
Byte register, you must write a decimal value that corresponds to the binary-
weighted sum of the corresponding bits.
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