HP 8340b User Manual

PLL3
THEORY
OF
OPERATION
PLL3
Assembly
•
A39
PLL3
upconverter.
The
PLL3
and
PLL1
phase-lock
loops
are
only used
when
in
CW
mode,
or
in
swept frequency
modes requiring
YIG
oscillator
(YO)
sweep
widths
less than
100
kHz.
Refer
to
Figure
C-1.
During
YO
sweep
widths of
100
kHz
to
5
MHz,
the
output
of
the
PLL2
VCO
(75
to
150
MHz)
is
divided
by
5
to
provide
a
15
to
30
MHz
output.
This
output
is
sent
directly
to the
YO
loop.
For
sweep
widths
less
than
100
kHz,
this
configuration provides
insufficient
resolution
(1
kHz)
to
set
the
start
frequency
to
closer
than
0.5%
of the
sweep
width.
To provide
finer
resolution,
the
output of
the
PLL2
VCO is
divided
further
(either
by
25
for
YO
sweep
widths
between
5
kHz and
100
kHz, or
by
500
for
YO
sweep
widths
less than
5
kHz).
The
frequency,
however,
is
also reduced
such
that
it
is
no
longer
in
the
20
to
30
MHz
range.
PLL1
and
PLL3
Loops translate
the
high
resolution,
low
frequency
PLL2
output
up
to
a
200
to
300
MHz
range.
Since
frequency
translation
is a
fixed offset
in
frequency,
it
does
not
change
the
resolution
or
sweep
width.
After
the
frequency
translation,
the
output
of
PLL1
is
divided
by
ten
to
reduce
the
200-300
MHz signal
to
20-30
MHz.
This
also
increases
the
output resolution
by
a
factor
of
ten.
The
A39
PLL3
assembly
mixes
160
MHz
with
the
output
of the
A40 PLL2
VCO,
and
outputs
the
sum
of
the
two
frequencies.
This
Is
done
using
a
phase-lock
loop
with
a
closed-loop
bandwidth of
approximately
10
kHz.
PLL3
uses
a
reference
signal
from
the
100
MHz
VCXO
reference
to
generate
the
160
MHz
offsetting
frequency.
As the
PLL2
output changes
frequency,
the
PLL3
output
also
changes frequency
with
the
same
resolution and
sweep
width,
but
at
a
higher
operating
frequency.
Frequency
Multiplier
x
1.6.
A
160
MHz
reference
signal
is
required
to
offset the
PLL2
output
by
160
MHz.
The
frequency
multiplier
X
1.6 generates
160
MHz
by
dividing
the
100
MHz input
reference
signal
by
five
and then
selecting
the
eighth
harmonic.
Mixer.
The
mixer
output
is
amplified,
filtered, and
sent
to the
phase/frequency
detector.
The
desired
mixer
output
is
the
difference
frequency
and
is
between
150
kHz
and
6
Mhz.
Phase/Frequency Detector.
The
phase/frequency
detector
generates
a
differential
output
signal
that
is
used
by
the
loop
amplifier
and
the
phase
lock
indicator.
C-6
20-30
Loops Overall
Theory
of
Operation
HP
8340B/41B

HP 8340b Specifications

General

Brand	HP
Model	8340b
Category	Inverter
Language	English