HP 8340b User Manual

Loop
Amplifier.
The
phase
detector
differential
outputs
are
the
loop amplifier
inputs.
Each
of
the
differential
inputs
is
passed
through
identical
low-pass
filters
and
a
voltage divider/filter. The output
of
the
voltage
divider
is
sent
to
a
varactor
diode
that
tunes
the
VCO.
160
to
166
MHz
VCO.
The
160
to
166
MHz
VCO
is
a
varactor-tuned oscillator.
A
buffer
transistor
output
provides
a 160
to
166
MHz
signal
that
drives
the
mixer.
Phase
Lock
Indicator.
The
phase
lock
indicator
senses
the
outputs
of
the
phase
detector
to
deter¬
mine
when
the
loop
is
locked.
The
ON
=
LOCKED
LED
indicates
a
phase
locked
condition.
PLL1
THEORY
OF OPERATION
PLL1
Assemblies
•
A36
PLL1
VCO
•
A37
PLL1
divider
•
A38
PLL1
IP
The
PLL1
and
PLL3
phase-lock
loops
are
only
used
when
in
CW
Mode, or
in
swept
frequency
modes
with
YIG
oscillator
(YO)
sweep
widths
less than
100
kHz.
PLL1
is
a
frequency translator.
It
produces
a
20
to
30
MHz signal
that
is
phase-locked
to:
•
The 160.15
to
166
MHz output
of the
PLL3
upconverter
•
A
reference
signal
from
the
reference
loop.
The
20
to
30
MHz
output
signal
is
generated
by the
PLL1
VCO.
Refer to Figure
C-1.
The
PLL1
VCO
produces
a 199
to
300
MHz
signal.
This
is
divided
by
10
to
produce
the
20-30
MHz signal required
by
the
YO
loop.
The
PLL1
feedback
loop phase-locks
the
VCO
to
the
PLL3
upconverter's
output,
and to
a
reference
signal from
the
reference loop.
The
feedback/phase
lock
loop
contains
the
A37
PLL1
divider and
the
A38
PLL1
IF
(mixer).
The
PLL1
IF
(mixer)
phase-locks
the
VCO
to
the
PLL3
output.
The 160.15 to
166
MHz
PLL3
output
is
mixed
with the
199
to
300
MHz
output
of the
PLL1
VCO.
The
IF
signal (36
to 139.7
MHz)
is
divided
by
two
(18
to
69.85
MHz).
This
IF
signal
is
phase/frequency
compared
to
a
fixed
5
MHz
reference
signal,
even
though
the
IF
frequency
may
be
sweeping.
A
microprocessor-controlled
fractional
divider divides the
IF signal
by
a
number
between
3.6
to
13.97.
This
produces
a
fixed
5
MHz
output
which
retains
the
phase/frequency
errors
from
the
PLL1
VCO.
The
10
MHz
reference
signal
is
divided by
two,
the
resultant
5
MHz
reference
signal
phase/frequency
compared
with the
output
of
the
fractional divider, and
the
error
voltage
is
sent
to the
PLL1
VCO.
This
completes
the
phase-lock
loop.
HP
8340B/41B
20-30
Loops
Overall
Theory
of
Operation
C-7

HP 8340b Specifications

General

Brand	HP
Model	8340b
Category	Inverter
Language	English