I/O
CHRDY
I
I/O
Channel Ready: This line (nonnally high
or
"READY")
is
pulled low
("NOT
READY")
by a memory
or
I/O
device to
lengthen
I/O
or memory cycles.
It
allows
slower devices to attach to the
I/O
Channel
with a minimum
of
difficulty. Any slow device
using this line should drive it low immediately
upon detecting a valid address and a Read or
write command. This line should never
be
held
low
for any period
in
excess of
10
clock cycles
(2.1 usec.) Machine cycles
(I/O
or memory)
are extended by an integral number
of
CLK
cycles (210 ns).
IRQ2-IRQ7 I
Interrupt Request 2 to
7:
These lines are used to
signal the processor that an
I/O
device requires
attention. They are prioritized with IRQ2
as
the highest priority and IRQ7 as the lowest. An
Interrupt Request is generated by raising an
IRQ
line (Low to High) and holding it high until
it
is
acknowledged by the processor (Interrupt
Service Routine).
~
lOR
0
-I/O
Read Command: This command line
in-
structs an
I/O
device to drive its data onto the
data bus.
It
may be driven
by
the processor or
the
DMA
Controller. This signal is active
LOW.
lOW
0
-I/O
Write Command: This command line
instructs an
I/O
device to read the data on the
data bus.
It
may be driven by the processor or
the
DMA
controller. This signal
is
active LOW.
MEMR
-Memory Read Command: This command line
instructs the memory to drive its data onto the
data bus.
It
may be driven by the processor or
the
DMA
Controller. This signal
is
active LOW.
MEMW
0
-Memory Write Command: This command
line instructs the memory to store the data
~
present on the data bus.
It
may
be
driven by
the processor
or
the
DMA
Controller. This
signal is active LOW.
2-11
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