Design and Environmental Specifications Intel® Server Board S1200BT TPS
Revision 1.0
Intel order number G13326-003
Table 53. Turn On/Off Timing
Delay from AC being applied to 5 VSB being
within regulation.
Delay from AC being applied to all output
voltages being within regulation.
Duration for which all output voltages stay within
regulation after loss of AC. Measured at 80% of
maximum load.
Delay from loss of AC to de-assertion of PWOK.
Measured at 80% of maximum load.
Delay from PSON# active to output voltages
within regulation limits.
Delay from PSON# deactive to PWOK being de-
asserted.
Delay from output voltages within regulation limits
to PWOK asserted at turn on.
Delay from PWOK de-asserted to output voltages
(3.3 V, 5 V, 12 V, -12 V) dropping out of
regulation limits.
Duration of PWOK being in the de-asserted state
during an off/on cycle using AC or the PSON
signal.
Delay from 5 VSB being in regulation to O/Ps
being in regulation at AC turn on.
Duration for which the 5 VSB output voltage stays
within regulation after loss of AC.
Figure 50. Turn On/Off Timing (Power Supply Signals)
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