Platform Management Intel® Server Board S1200BT TPS
Revision 1.0
Intel order number G13326-003
4. Platform Management
This chapter is only for The Intel
®
Server Board S1200BTL.
The platform management subsystem is based on the Integrated BMC features of the
ServerEngines* Pilot III. The onboard platform management subsystem consists of
communication buses, sensors, system BIOS, and server management firmware. The following
diagram provides an overview of the Server Management Bus (SMBUS) architecture used on
this server board.
BB Sensor4
Temp: 0x96
PATSBURG -A/D
IBMC
SMLink1 @ 100kHz (3.3V STBY)
MM/S[7]
SMLink0 @ 400kHz (3.3V STBY)
MM[1]
MM[4]
PMBus PS 0
FRU: 0xA0 / Device:
0xB0
S
PMBus (3.3V STBY)
MM[5]
HSBP (3.3V STBY)
MM[2]
PCI (3.3V STBY)
ME
PCH
0x88
(0x88 is default for SSB)
M/S
MM[0]
0xTBD
MM/S[1]
0xTBD
PMBus PS 1
FRU: 0xA2 / Device:
0xB2
S
PCI/PCIe Slots
S
CK-MNG
0xD0
S
CK420BQ
0xD2
S
DB1900Z
0xD8
S
Host (3.3V Main)Host (3.3V STBY)
MM[3]
MM[6]
XDP 0
N/A
MM
XDP 1
N/A
MM
S SMBus Slave (Main)
M/S
MM
MM/S
SMBus Multi-Master (Main)
SMBus Multi-Master (Standby)
SMBus Master (Main)
S SMBus Slave (Standby)
MM[0]
IPMB (3.3V STBY)
Voltage
Translation
LCP
0x22
S
IPMB Connector
M/S
IPMB (5V STBY)
BB sensor2
Temp: 0x98
S
ISOLATION
0-Ω
STUFFED
Sensor (3.3V STBY)
Front-Panel
FRU: 0xAE
S
BB Sensor1
Temp: 0x9A
S
BB Sensor3
Temp: 0x9C
S
Riser1
FRU: 0xA0
Temp: 0x90
S
Riser2
FRU: 0xA2
Temp: 0x92
S
rIOM
FRU: 0xA4
Temp: 0x94
S
SAS Module
FRU: 0xA6
Temp: 0x96
S
S
Front-Panel
Temp: 0x9E
S
ISOLATION
HSBP1
PSOC 0xD0
Temp: 0x90
FRU: 0xA0
HSBP2
PSOC 0xD6
Temp: 0x96
FRU: 0xA6
HSBP3
PSOC 0xD4
Temp: 0x94
FRU: 0xA4
S
S
S
Lewsville
0xC8 (Bromollow)
S
Nuvoton LOT6
0x6C
BB Optional
sensor 5
Temp: 0x94
S
Note: This sensor5 address is optional
only reserved for possible Thermal
management on certain board such as
IronPass
Note: The SMBus to PCIE slot connection is
reserved for certain cased which will use it for
GPU management.
Figure 14. Server Management Bus (SMBUS) Block Diagram
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