revert back to voltage level. The output of U309 then
represents the selected compliance voltage scaled down by a
factor of 20.
This signal and its inverse KJ309A, R324 and R327) are ap-
plied to divider network R331 and R336 which are referenced
to output common. At the junction of each divider network is
an amplifier which reverts the previous scaling factor.
Resulting from this is an error voltage approximately equal to
the difference between the actual compliance voltage level
and the programmed level. Each amplifier U307A and B and
the associated circuitry, is coupled through diodes CR303
and CR302 on R333. The polarity of the diodes is arranged
such that a voltage is impressed on R333 only when the ac-
tual voltage compliance exceeds + the programmed value.
This result is applied to the output mode via low leakage
diode CR304 preventing any further voltage excursion. Cur-
rent from the range resistors is shunted through diodes
CR305 and CR306 when this operation occurs. Resistors
R330 and R332 add an offset to compensate for diode drops
in CR302 through CR304.
The circuit configuration of U313A and B comprise a window
comparator to detect a V-limit condition across R333. The
comparator limits are set by resistor divider network R338
through R341. U313A and B open collector outputs are con-
figured in a “wire ORed” fashion through pull up resistor
R346. When ever the voltage across R333 exceeds the com-
parator limits, a logical 1 is developed through current limiting
resistor R347 to the output of invetter U316E. C311 is used
for stabilization.
VR301 supplies the digital circuitry with the required +5V.
This voltage is also supplied to the digital board for use by the
optically isolated portion of the circuitry.
4.5 DIGITAL BOARD (Microcomputer)
To facilitate understanding of the following discussion refer
to schematic diagram 220-106 (sheet 1 of 2). For an overall
block diagram of the digital circuitry refer to Figure 4-2.
The microcomputer and its associated logic circuitry, controls
front panel functions (source, time, auto, etc.), operation of
the front panel display and data through the IEEE-488 inter-
face circuitn/ when it is installed.
The microcomputer includes a 6808 microprocessing unit
U115; a 6522 versatile interface adapter U114; two 2732
ROMs U109 and Ulll; four 2114 RAMS UlOl, U103, U105
and U107; an address decoder UllO; a data bus driver U116
and the necessary reset logic. The memory utilized in this
system is shown in the memory map (Figure 4-3). Using ad-
dress lines A13, Al4 and A15; UllO sections the 64k of
memory space into 8k and 4k segments. The total memory
used is a small portion of the entire addressing capabilities of
the 6808 microprocessor U115. Memory location for the 64k
addresses are assigned the values 0000,s through FFFF,,.
Interfacing of the microprocessor with the RAMS, ROMs,
Front Panel, VIA or the IEEE-488 interface ciruitry is con-
trolled by the address decoder, UllO.
Partial address decoding is used in this system. The function
selected is determined by the state of the address lines A13,
Al4 and A15. These address lines determine which output is
selected at the decoder Ul 10 in accordance with the memory
map. Only one of the devices (RAM, ROM VIA etc.) will have
access to the data bus at any time. The address decoder
selects one of the devices only after a Valid Memory Address
(VMA) has been asserted at the decoders input EN (pin 6).
The VMA signal is generated by the 6808 microprocessor.
Timing for the computing sequence is provided by the 4MHz
crystal YlOl . The 6808 microprocessor divides this signal by
four to obtain IMHz signal at the 2 output (pin 37).
U102, U104, UlO6C, U108C and their associated circuitry
form a reset network (watch dog) which resets the
microprocessor, VIA and the IEEE-488 interface (when in-
stalled). The circuit actuates in the event the front panel
display is not updated after a specific period of time has
elapsed due to a lost program or power line transient.
4-2
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