National Instruments PCIe-6323 User Manual

© National Instruments | 7-35
X Series User Manual
In software, program the frequency generator as you would program one of the counters for
pulse train generation.
For information about connecting counter signals, refer to the
Default Counter/Timer Pins
section.
Frequency Division
The counters can generate a signal with a frequency that is a fraction of an input signal. This
function is equivalent to continuous pulse train generation. Refer to the
Continuous Pulse Train
Generation
section for detailed information.
For information about connecting counter signals, refer to the
Default Counter/Timer Pins
section.
Pulse Generation for ETS
In the equivalent time sampling (ETS) application, the counter produces a pulse on the output a
specified delay after an active edge on Gate. After each active edge on Gate, the counter
cumulatively increments the delay between the Gate and the pulse on the output by a specified
amount. Thus, the delay between the Gate and the pulse produced successively increases.
The increase in the delay value can be between 0 and 255. For instance, if you specify the
increment to be 10, the delay between the active Gate edge and the pulse on the output increases
by 10 every time a new pulse is generated.
Suppose you program your counter to generate pulses with a delay of 100 and pulse width of 200
each time it receives a trigger. Furthermore, suppose you specify the delay increment to be 10.
On the first trigger, your pulse delay is 100, on the second it is 110, on the third it is 120; the
process repeats until the counter is disarmed. The counter ignores any Gate edge that is received
while the pulse triggered by the previous Gate edge is in progress.
The waveform thus produced at the counter’s output can be used to provide timing for
undersampling applications where a digitizing system can sample repetitive waveforms that are
higher in frequency than the Nyquist frequency of the system. Figure 7-38 shows an example of
pulse generation for ETS; the delay from the trigger to the pulse increases after each subsequent
Gate active edge.
Figure 7-38. Pulse Generation for ETS
OUT
D1 D2 = D1 + ∆DD3 = D1 + 2∆D
GATE

National Instruments PCIe-6323 Specifications

General

Brand	National Instruments
Model	PCIe-6323
Category	I/O Systems
Language	English