Omron SYSMAC CP2E-N D Series User Manual

11-7
11 High-speed Counters
CP2E CPU Unit Software User’s Manual(W614)
11-1 Overview
11
11-1-3 Specifications
11-1-3 Specifications
Item Description
Pulse input method
(Counting mode)
Increment pulse
inputs
Differential phase
inputs (×4)
Up/down pulse
inputs
Pulse + direction
inputs
Input signal Increment Phase-A Up pulse Pulse
− Phase-B Down pulse Direction
− Phase-Z Reset Reset
Frequency
and number
of high-
speed
counters
E/S-type
CPU Unit
100 kHz:
2 counters
10 kHz: 4 counters
50 kHz: 1 counter
5 kHz: 1 counter
100 kHz: 1 counter
10 kHz: 1 counter
100 kHz:
2 counters
N14/20 CPU
Unit
100 kHz:
2 counters
10 kHz: 4 counters
50 kHz: 1 counter
5 kHz: 1 counter
100 kHz: 1 counter
10 kHz: 1 counter
100 kHz:
2 counters
N30/40/60
CPU Unit
100 kHz:
3 counters
10 kHz: 3 counters
50 kHz: 2 counters 100 kHz: 2 counters 100 kHz:
2 counters
Counting mode Linear mode or circular (ring) mode
Count values Linear mode: 8000 0000 to 7FFF FFFF hex
Ring Mode: 0000 0000 to Ring SV
High-speed counter PV
storage locations
High-speed counter 0: A271 (upper 4 digits) and A270 (lower 4 digits)
High-speed counter 1: A273 (upper 4 digits) and A272 (lower 4 digits)
High-speed counter 2: A317 (upper 4 digits) and A316 (lower 4 digits)
High-speed counter 3: A319 (upper 4 digits) and A318 (lower 4 digits)
High-speed counter 4: A323 (upper 4 digits) and A322 (lower 4 digits)
High-speed counter 5: A325 (upper 4 digits) and A324 (lower 4 digits)
The PVs are refreshed in the overseeing processes at the start of each cycle. Use
PRV to read the most recent PVs.
Data format: 8 digit hexadecimal
• Range in linear mode: 8000
0000 to 7FFF FFFF hex
• Range in Ring Mode: 0000 0000 to Ring SV (Circular Max. Count)
Control
method
Target value
comparison
Up to 6 target values and corresponding interrupt task numbers can be registered.
Range
comparison
Up to 6 ranges can be registered, with a separate upper limit, lower limit, and inter-
rupt task number for each range.
Counter reset method • Phase-Z + Software reset
The high-speed counter is reset when the phase-Z signal goes ON while the
Reset Bit (A531.00 to A531.05) is ON. (Phase Z cannot be used for the incre-
ment pulse.)
• Software reset
The high-speed counter is reset when the Reset Bit (A531.00 to A531.05) is
turned ON.
Operation can be set to stop or continue the comparison operation when the high-
speed counter is reset.

Omron SYSMAC CP2E-N D Series Specifications

General

Brand	Omron
Model	SYSMAC CP2E-N D Series
Category	Computer Hardware
Language	English