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Multi-address Monitoring
0Ć000
0Ć000
TIM 00
0 T 00
0100
0 0000 T 00
0100
0 0001 T 00
0100
0 0001 T 00
^OFF 0100
0 cD00 0001 T 00
10FF ^OFF 0100
0 cD00 0001 T 00
10FF ^OFF 0100
0 T 00 cD00 0001
0100 10FF OFF
0 cD00 0001
10FF ^OFF
0 0001
^OFF
0Ć000
CONT 0001
Cancels monitoring of
leftmost address
Cancels Monitor
operation
or
4-1-2 Force Set/Reset
When the Bit/Multibit Monitor operation is being performed and a bit, timer, or
counter address is leftmost on the display, CHG and ENT can be pressed to
turn ON/OFF the bit, start/reset the timer, or increment/reset the counter.
Timers will not operate in PROGRAM mode. Dedicated flags and bits cannot
be turned ON and OFF with this operation.
Bit status will remain ON or OFF until the I/O bit status is refreshed, which
occurs each scan. Hence, forced status will be canceled at each I/O refresh.
If a timer is started, the Completion Flag for it will be turned ON when SV has
been reached.
This operation can be used in RUN mode to check wiring of outputs from the
PC prior to actual program execution.
Key Sequence
Bit/word Monitor
Mutlibit/word Monitor
Monitoring Operation and Modifying Data Section 4-1
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