Quectel LPWA Series Hardware Design

LPWA Module Series
BG950A-GL&BG951A-GL_Hardware_Design
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2.5. Pin Description
The following table shows the DC characteristics and pin descriptions.
Table 5: I/O Parameters Definition
1. ADC input voltage must not exceed 1.8 V.
2. Keep all RESERVED pins and unused pins unconnected.
3. GND pins should be connected to ground in the design.
4. PCM and I2C interfaces are for VoLTE* only.
5. Only BG950A-GL supports GNSS_LNA_EN (pin 51) and VDD_RF (pin 99).
6. For BG950A-GL, pin27 and pin28 can only be used as AUX_TXD and AUX_RXD.
7. The pin assignment of BG951A-GL will be added in the future version.
Type
Description
AI
Analog Input
AIO
Analog Input/Output
DI
Digital Input
DO
Digital Output
DIO
Digital Input/Output
OD
Open Drain
PI
Power Input
PO
Power Output
NOTE

Quectel LPWA Series Specifications

General

Brand	Quectel
Model	LPWA Series
Category	GSM/GPRS Modules
Language	English