Quectel LPWA Series Hardware Design

LPWA Module Series
BG950A-GL&BG951A-GL_Hardware_Design
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The voltage value on ADC pins can be read via AT+QADC=<port>:

AT+QADC=0: read the voltage value on ADC0

AT+QADC=1: read the voltage value on ADC1
For more details about the AT command, see document [3].
The resolution of the ADC is up to 12 bits. The following table describes the characteristic of the ADC
interface.
Table 21: Characteristics of ADC Interface
4.6. Indication Signal
4.6.1. PSM Status Indication*
Table 22: Pin Definition of PSM_IND
When PSM is enabled, the function of PSM_IND pin will be activated after the module is rebooted. When
PSM_IND is in high voltage level, the module is in normal operation state. When it is in low level, the
module is in PSM.
Name
Min.
Typ.
Max.
Unit
Voltage Range
0
-
1.8
V
Resolution
6
-
12
bit
Input Resistance
-
-
TBD
KΩ
1. ADC input voltage must not exceed 1.8 V.
2. It is prohibited to supply any voltage to ADC pin when VBAT is removed.
3. It is recommended to use resistor divider circuit for ADC application, and the divider’s resistor
accuracy should be no less than 1 %.
Pin Name
Pin No.
I/O
Description
Comment
PSM_IND
1
DO
Indicate the module’s power saving mode
1.8 V power domain.
If unused, keep this pin
open.
NOTE

Quectel LPWA Series Specifications

General

Brand	Quectel
Model	LPWA Series
Category	GSM/GPRS Modules
Language	English