Quectel LPWA Series Hardware Design

LPWA Module Series
BG950A-GL&BG951A-GL_Hardware_Design
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4.4. UART Interfaces
Pin definition of the UART interface is shown as follows:
Table 16: Pin Definition of Main UART Interface
The module provides three UART interfaces and the following shows their features:
Table 17: UART Information
Pin Name
Pin No.
I/O
Description
Comment
MAIN_DTR
30
DI
Main UART data terminal ready
1.8 V power domain
If unused, keep this pin open.
MAIN_RXD
34
DI
Main UART receive
MAIN_TXD
35
DO
Main UART transmit
MAIN_CTS
36
DO
Main UART clear to send
MAIN_RTS
37
DI
Main UART request to send
MAIN_DCD
38
DO
Main UART data carrier detect
MAIN_RI
39
DO
Main UART ring indication
Parameters
Main UART Interface
Debug UART Interface
Auxiliary UART
Interface
Supported Baud
Rate
9600 bps, 19200 bps,
38400 bps, 57600 bps,
115200 bps, 230400 bps,
460800 bps, 921600 bps
and 3000000 bps
9600 bps, 19200 bps,
38400 bps, 57600 bps,
115200 bps, 230400 bps,
460800 bps, 921600 bps
and 3000000 bps
-
Default Baud Rate
115200 bps
115200 bps
921600 bps
Default frame format
8N1 (8 data bits, no parity,
1 stop bit)
8N1 (8 data bits, no parity,
1 stop bit).
8N1 (8 data bits, no
parity, 1 stop bit).
Functions

Data transmission

AT command
communication

RTS and CTS
hardware flow control

Firmware upgrade

Software debugging

Log output

RF calibration

Log output

Quectel LPWA Series Specifications

General

Brand	Quectel
Model	LPWA Series
Category	GSM/GPRS Modules
Language	English