Renesas RZ Series User Manual

RZ/G, RZ/V
Series
RZ Family / RZ/G, RZ/A Series 2. Functional Specifications
R01UH0990EJ0101 Rev.1.01 Page 49 of 83
Jul 28, 2022
2.6 Clock Configuration
Figure 2.7 shows a block diagram of the Clock configuration.
NOTE
SD Interface supports UHS-I mode of 50MB/s (SDR50) and 104MB/s (SDR104).
DIFF1
DDR4_SDRAM
VCC
CK_T
XI
XI
CLKIN_X2 DIFF2
DIFF1B
SE2
CLKINB_X1 REF
SE1
EXCLK
TCK/SWDCLK
AUDIO_CLK1
AUDIO_CLK2
DDR_CLK_P
DDR_CLK_N
QSPI0_SPCLK
SD1_CLK
SD0_CLK
RZ/G2UL
Ethernet0 PHY
Ethernet1 PHY
CLK
eMMC memory
CLK
SD0 card slot
CK_C
CLK
JTAG
XI
QSPI flash memory
SD1 card slot
Camera connector
MIPI_CLK_P
MIPI_CLK_N
HDMI transceiver
DRXC_P
DRXC_N
CSI_CLK_P
SSI1_BCK
RIIC0_SCL
RSPI1_CK
RIIC1_SCL
SCLK/MCLK
CAM_I2C_SCL
SCL
CSI_CLK_N
PMOD0
SCK
X1 24MHz
24MHz
11.2896MHz
12.2880MHz
11.2896MHz
Max. 125MHz
Max. 800MHz
MCLK
Audio Codec
BCLK
SCLK
Max. 33.33MHz
(SDR 3.3V)
Max.133MHz
Max. 66MHz
(SDR mode)
20MHz
Max. 33.33MHz (SDR 3.3V)
Max. 1.5GHz
Max. 1MHz
Max. 1MHz
Max. 12.5MHz
Max. 10MHz
CECCLK
CLK
CMOS Oscillator
12MHz
Clock IC
Max. 125MHz
Note: shows the Carrier Board
PMOD1
SCL
VCC
OctaFlash
VCC
OctaRAM
Max. 100MHz
(SDR mode)
Figure 2.7 Block Diagram of Clock Configuration
RZ/A3UL SMARC Module Board
OCTAL Edition
RZ/A3UL SMARC Module Board
QSPI Edition
RZ/G2UL SMARC Module Board
RZ/Five SMARC Module Board

Renesas RZ Series Specifications

General

Brand	Renesas
Model	RZ Series
Category	Computer Hardware
Language	English