Latch
Generate
SOC
pulse
when
input=1
2-bit
Counter
Set
Clear
ClearCNT
IncCNT
ETPS[SOCACNT]
ETPS[SOCAPRD]
ETCLR[SOCA]
SOCA
ETFRC[SOCA]
ETSEL[SOCAEN]
ETFLG[SOCA]
ETSEL[SOCASEL]
000
001
010
011
100
101
111
101
0
0
CTRU=CMPA
CTRD=CMPA
CTRU=CMPB
CTRD=CMPB
CTR=Zero
CTR=PRD
Latch
Generate
SOC
pulse
when
input=1
2-bit
Counter
Set
Clear
ClearCNT
IncCNT
ETPS[SOCBCNT]
ETPS[SOCBPRD]
ETCLR[SOCB]
SOCB
ETFRC[SOCB]
ETSEL[SOCBEN]
ETFLG[SOCB]
ETSEL[SOCBSEL]
000
001
010
011
100
101
111
101
0
0
CTRU=CMPA
CTRD=CMPA
CTRU=CMPB
CTRD=CMPB
CTR=Zero
CTR=PRD
Event-Trigger (ET) Submodule
Figure 2-42. Event-Trigger SOCA Pulse Generator
Figure 2-43 shows the operation of the event-trigger's start-of-conversion-B (SOCB) pulse generator. The
event-trigger's SOCB pulse generator operates the same way as the SOCA.
Figure 2-43. Event-Trigger SOCB Pulse Generator
SPRU791D – November 2004 – Revised October 2007 ePWM Submodules 67
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