Stacked RJ45
SGMII
Top ± P3
Bottom ± P2
Stacked RJ45
SGMII
Top ± P1
Bottom ± P0
Quad-SGMII
PHY
Clock
Gen
ENET EXP Mating Conn
J721E EVM Overview
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12
SPRUIS4A–December 2019–Revised May 2020
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Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM)
Because the Jacinto7 Common Processor board is used with different SOM boards featuring different
Jacinto7 processors with different feature sets, some of the board’s peripherals/interfaces may not be
supported. For the J721E SOM, the following interfaces are not supported:
• USB 3.0 uAB (USB Type C, and 2x USB Type A interfaces are supported)
• 2nd DisplayPort interface (single DisplayPort interface is supported)
These interfaces are identified with a grey color in the component placement pictures (opposed to the
yellow color).
2.4 Quad Ethernet Components Identification
Figure 7. Quad Ethernet Component Identification
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