MODE Selection
See “R3” in table
See “R4” in table
Selected Mode: 0
(Default)
Software Config Only
LFMODE (15 – <85 MHz)
REPEATER (OFF)
BACK-COMPATIBLE (OFF)
I2S–B OFF. 24B RGB
LFMODE (15 – <85 MHz)
REPEATER (OFF)
BACK-COMPATIBLE (OFF)
I2S–B OFF. 24B RGB
R3 = <open>
R4 = 40.2K, 1% (or any)
R3 = <open>
R4 = 40.2K, 1% (or any)
See “R1” in table
See “R2” in table
7b’ I2C Address
R1
R2
0x2C
Open
40.2K
(other – see DM)
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J721E EVM Hardware Architecture
65
SPRUIS4A–December 2019–Revised May 2020
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Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM)
4.14 FPD Interface (Audio Deserializer)
CP Board supports TI ‘s FPD Link III De-serializer IC Mfr. Part# DS90UB926QSQE for recover the audio
signals from Tuner interface using HSD connector Mfr. Part# D4S20G-400A5-C. The de-serializer will
recover up to eight digital audio channels plus I2C channel across digital link.
This audio signal shall be connected to McASP11 port of J721E SoC through 1:3 DEMUX
(SN74CBT16214CDGGR). The channel selection is supported by both GPIO expander and EVM
configuration DIP switch (SW3).
The I2C3 signals of J721E being used for controlling of the De-serializer. A 40.2KΩ pull down is provided
on ID[X] pin to set the 7‘b I2C address to 0x2C.
Figure 49. FPD-Link UB926 ID Setting Circuit
Power +12 V is provided to the HSD connector using a power switch TPS1H100AQPWPRQ1 to power the
FPD Link-III Tuner expansion board. The power switch is controlled by a GPIO expander signal
(UB926_PWR_SW_CNTRL).
Figure 50 shows the mode selection for the de-serializer.
Figure 50. FPD-Link UB926 Mode Selection Circuit
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