240
1 k
RZQ
240
DDR_DQ[31:24]
DDR_DM3
DDR_DQS3P
DDR_DQS3N
DDR_DQ[23:16]
DOR_DM2
DDR_DQS2P
DDR_DQS2N
DDR0_CSN0_1
DDR0_CSN1_1
DDR0_CKE1
DDR_DQ[15:8]
DDR_DM1
DDR_DQS1P
DDR_DQS1N
DDR_DQ[7:0]
DDR_DM0
DDR_DQS0P
DDR_DQS0N
DDR0_CA[5:0]
DDR0_CSN0_0
DDR0_CSN1_0
DDR0_CKE0
DDR0_CK_T
DDR0_CK_C
DDR0_RESETn
DDR0_CAL
DDR_RET
VDD2
VDD2
VDDQ
ZQ
ODTCA_A
1
ODTCA_B
1
DQ[15:8]_B
DM[1]_B
DQS[1]_t_B
DQS[1]_c_B
DQ(7:]_B
DM(0]_B
DQS(0]_t_B
DQS(0]_c_B
CA[5:0]_B
CS0_B
CS1_B
CKE0_B
CKE1_B
CK_1_B
CK_c_B
DQ[15:8]_A
DM[1]_A
DQS[1]_t_A
DQS[1]_c_A
DQ(7:0]_A
DM(0]_A
DQS(0]_t_A
DQS(0]_c_A
CA[5:0]_A
CS0_A
CS1_A
CKE0_A
CKE1_A
CK_t_A
CK_c_A
RESET_n
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J721E EVM Hardware Architecture
43
SPRUIS4A–December 2019–Revised May 2020
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Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM)
4.8 Memory interfaces
4.8.1 LPDDR4 Interface
The J721E SOM has 4GB of LPDDR4 using single 32Gb x 8-bit wide memory devices arranged in an 32-
bit wide bus. The LPDDR4 interface can operate up to 3733 Mb/s speed. The LPDDR4 device is
connected using T-branched routing for the clock and address/command lines and point-to-point
connection for the data bus.
The Micron’s LPDDR4 memory chip MT53D1024M32D4DT is used on the SoM, it requires 1.8 V for Core
(VDD1), 1.1 V for Core2 (VDD2) and 1.1 V or 0.6 V for I/O buffer power (VDDQ). The VDDQ supplies are
selected using a dip switch SW1 on the SoM. For more details, see Section 4.5.3.
Figure 25. J721E SoM LPDDR4
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