DAC
Recovered
³GLUW\´FORFNRU
clean clock
0XOWLSOH³FOHDQ´
clocks at different
frequencies
DCLKout0 &
DCLKout2
DCLKout12
DCLKout4,
SDCLKout5
FPGA
CLKin0
Crystal or
VCXO
Backup
Reference
Clock
CLKin1
OSCout
DAC
SDCLKout1 &
SDCLKout3
ADC
LMX2581
PLL+VCO
Serializer/
Deserializer
LMK0482xB
SDCLKout13
SDCLKout9 &
SDCLKout11
DCLKout8 &
DCLKout10
LMK04821
,
LMK04826
,
LMK04828
SNAS605AR –MARCH 2013–REVISED DECEMBER 2015
LMK0482x Ultra Low-Noise JESD204B Compliant
Clock Jitter Cleaner with Dual Loop PLLs
1 Features 2 Applications
1
• JEDEC JESD204B Support
• Wireless Infrastructure
• Ultra-Low RMS Jitter • Data Converter Clocking
• Networking, SONET/SDH, DSLAM
– 88 fs RMS Jitter (12 kHz to 20 MHz)
• Medical / Video / Military / Aerospace
– 91 fs RMS Jitter (100 Hz to 20 MHz)
• Test and Measurement
– –162.5 dBc/Hz Noise Floor at 245.76 MHz
• Up to 14 Differential Device Clocks from PLL2
3 Description
– Up to 7 SYSREF Clocks
The LMK0482x family is the industry's highest
– Maximum Clock Output Frequency 3.1 GHz
performance clock conditioner with JEDEC
– LVPECL, LVDS, HSDS, LCPECL
JESD204B support.
Programmable Outputs from PLL2
The 14 clock outputs from PLL2 can be configured to
• Up to 1 Buffered VCXO/Crystal Output from PLL1
drive seven JESD204B converters or other logic
devices using device and SYSREF clocks. SYSREF
– LVPECL, LVDS, 2xLVCMOS Programmable
can be provided using both DC and AC coupling. Not
• Dual Loop PLLatinum™ PLL Architecture
limited to JESD204B applications, each of the 14
• PLL1
outputs can be individually configured as high
– Up to 3 Redundant Input Clocks
performance outputs for traditional clocking systems.
– Automatic and Manual Switch-Over Modes
The high performance combined with features like the
ability to trade off between power or performance,
– Hitless Switching and LOS
dual VCOs, dynamic digital delay, holdover, and
– Integrated Low-Noise Crystal Oscillator Circuit
glitchless analog delay make the LMK0482x family
– Holdover mode when Input Clocks are Lost
ideal for providing flexible high performance clocking
• PLL2
trees.
– Normalized [1 Hz] PLL Noise Floor of
Device Information
(1)
-227 dBc/Hz
PART VCO0
VCO1 FREQUENCY
– Phase Detector Rate up to 155 MHz
NUMBER FREQUENCY
– OSCin Frequency-Doubler
2920 to 3080 MHz
LMK04821 1930 to 2075 MHz VCO1 Div = ÷2 to ÷8
– Two Integrated Low-Noise VCOs
(÷2 = 1460 to 1540 MHz)
• 50% Duty Cycle Output Divides, 1 to 32
LMK04826B 1840 to 1970 MHz 2440 to 2505 MHz
(even and odd)
LMK04828B 2370 to 2630 MHz 2920 to 3080 MHz
• Precision Digital Delay, Dynamically Adjustable
(1) For all available packages, see the orderable addendum at
• 25 ps Step Analog Delay
the end of the datasheet.
• Multi-mode: Dual PLL, single PLL, and Clock
Simplified Schematic
Distribution
• Industrial Temperature Range: –40 to 85°C
• Supports 105°C PCB Temperature (Measured at
Thermal Pad)
• 3.15-V to 3.45-V Operation
• Package: 64-Pin QFN (9.0 mm x 9.0 mm x 0.8
mm)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
To Next Page
Need help?
General
