Texas Instruments LMK04828 User Manual

LMK04821 , LMK04826 , LMK04828
www.ti.com SNAS605AR –MARCH 2013–REVISED DECEMBER 2015
9.7.7.5 PLL1_WND_SIZE, PLL1_CP_TRI, PLL1_CP_POL, PLL1_CP_GAIN
This register controls the PLL1 phase detector.
Table 56. Register 0x15B
POR
BIT NAME DESCRIPTION
DEFAULT
PLL1_WND_SIZE sets the window size used for digital lock detect for PLL1. If the phase
error between the reference and feedback of PLL1 is less than specified time, then the
PLL1 lock counter increments.
Field Value Definition
7:6 PLL1_WND_SIZE 3
0 (0x00) 4 ns
1 (0x01) 9 ns
2 (0x02) 19 ns
3 (0x03) 43 ns
This bit allows for the PLL1 charge pump output pin, CPout1, to be placed into TRI-STATE.
5 PLL1_CP_TRI 0 0: PLL1 CPout1 is active
1: PLL1 CPout1 is at TRI-STATE
PLL1_CP_POL sets the charge pump polarity for PLL1. Many VCXOs use positive slope.
A positive slope VCXO increases output frequency with increasing voltage. A negative
4 PLL1_CP_POL 1 slope VCXO decreases output frequency with increasing voltage.
0: Negative Slope VCO/VCXO
1: Positive Slope VCO/VCXO
This bit programs the PLL1 charge pump output current level.
Field Value Gain
0 (0x00) 50 µA
1 (0x01) 150 µA
2 (0x02) 250 µA
3:0 PLL1_CP_GAIN 4
3 (0x03) 350 µA
4 (0x04) 450 µA
... ...
14 (0x0E) 1450 µA
15 (0x0F) 1550 µA
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Texas Instruments LMK04828 Specifications

General

Brand	Texas Instruments
Model	LMK04828
Category	Motherboard
Language	English