LMK04821
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LMK04826
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LMK04828
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SNAS605AR –MARCH 2013–REVISED DECEMBER 2015
9.7.8 (0x160 - 0x16E) PLL2 Configuration
9.7.8.1 PLL2_R[11:8], PLL2_R[7:0]
Table 61. PLL2_R[11:0]
MSB LSB
0x160[3:0] 0x161[7:0]
This register contains the value of the PLL2 R divider.
Table 62. Registers 0x160 and 0x161
BIT REGISTERS NAME POR DEFAULT DESCRIPTION
7:4 0x160 NA 0 Reserved
Valid values for the PLL2 R divider.
Field Value Divide Value
3:0 0x160 PLL2_R[11:8] 0
0 (0x00) Not Valid
1 (0x01) 1
2 (0x02) 2
3 (0x03) 3
7:0 0x161 PLL2_R[7:0] 2 ... ...
4,094 (0xFFE) 4,094
4,095 (0xFFF) 4,095
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