LMK04821
,
LMK04826
,
LMK04828
SNAS605AR –MARCH 2013–REVISED DECEMBER 2015
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9.7.7.3 CLKin2_R[13:8], CLKin2_R[7:0]
MSB LSB
0x157[5:0] 0x158[7:0]
Table 53. Registers 0x157 and 0x158
POR
BIT REGISTERS NAME DESCRIPTION
DEFAULT
7:6 0x157 NA 0 Reserved
The value of PLL1 N counter when CLKin2 is selected.
Field Value Divide Value
5:0 0x157 CLKin2_R[13:8] 0
0 (0x00) Reserved
1 (0x01) 1
2 (0x02) 2
... ...
7:0 0x158 CLKin2_R[7:0] 150
16382 (0x3FFE) 16382
16383 (0x3FFF) 16383
9.7.7.4 PLL1_N
Table 54. PLL1_N[13:8], PLL1_N[7:0]
PLL1_N[13:0]
MSB LSB
0x159[5:0] 0x15A[7:0]
These registers contain the N divider value for PLL1.
Table 55. Registers 0x159 and 0x15A
POR
BIT REGISTERS NAME DESCRIPTION
DEFAULT
7:6 0x159 NA 0 Reserved
The value of PLL1 N counter.
Field Value Divide Value
5:0 0x159 PLL1_N[13:8] 0
0 (0x00) Not Valid
1 (0x01) 1
2 (0x02) 2
7:0 0x15A PLL1_N[7:0] 120 ... ...
4,095 (0xFFF) 4,095
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