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J721E EVM Hardware Architecture
59
SPRUIS4A–December 2019–Revised May 2020
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Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM)
4.11.3 M.2 PCIe Interface
Common Processor board supports 2 Lane PCIe M2.0 standard, to interface external SSD device.
Figure 40. PCIe Interface for SERDES2
M.2 series receptacle with M-Keyed Mfr. Part# MDT320M01001 is used to attach the external SSD device
on common processor board. The x2 lane PCIe interface signals SERDES2 of J721E SoC will be
terminated with receptacle. SoC_I2C0 is used for SMBUS access. Voltage level translator
(TCA9543APWR) circuit will be used to change the I/O level of SMBUS signals to 1.8 V. The link
activation signal (WKUP) from PCIe connector is terminated to the test point TP85.
Reset: Reset signal to the SSD/add on module is controlled by GPIO expander. The GPIO signal is pulled
low with a resistor 10K by default to ensure PCIe Reset (#PERST) remains asserted until SoC releases
reset.
Clock: A clock generator (CDCI #2) is provided to drive 100MHz HCSL clock for PCIe add on cards and
J721E SoC. Resistor options are provided to select the clock source either from SoC or clock generator.
4.12 USB Interface
The Common Processor Board includes the following USB interfaces:
• One USB 3.1 Type C interface using TUSB321RWBR and PTPS25830QWRHBTQ1 PD controller
• Four USB 2.0 Interfaces using USB Hub (TUSB4041IPAPR)
• (Not supported in J721E SoC) One USB 3.0 Micro AB connector. It is reserved for future J7 family
devices.
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