9.4 Device Functional Modes
9.4.1 Boot Code
The TPS65982 has a Power-on-Reset (POR) circuit that monitors LDO_3V3 and issues an internal reset signal.
The digital core, memory banks, and peripherals receive clock and RESET interrupt is issued to the digital core
and the boot code starts executing. Figure 9-54 provides the TPS65982 boot code sequence.
The TPS65982 boot code is loaded from OTP on POR, and begins initializing TPS65982 settings. This
initialization includes enabling and resetting internal registers, loading trim values, waiting for the trim values
to settle, and configuring the device I
2
C addresses.
The unique I
2
C address is based on the customer programmable OTP, DEBUG_CTLX pins, and resistor
configuration on the I2C_ADDR pin.
Once initial device configuration is complete the boot code determines if the TPS65982 is booting under dead
battery condition (VIN_3V3 invalid, VBUS valid). If the boot code determines the TPS65982 is booting under
dead battery condition, the BUSPOWERZ pin is sampled to determine the appropriate path for routing VBUS
power to the system.
VIN_3V3 or VBUS
Application
Initialize
Configure I C
2
Dead Battery
Check
Load Appcode
Load from SPI
Flash
Download from
UART
SPI_POCI High
SPI_POCI Low
Figure 9-54. Flow Diagram for Boot Code Sequence
9.4.2 Initialization
During initialization the TPS65982 enables device internal hardware and loads default configurations. The
48-MHz clock is enabled and the TPS65982 persistence counters begin monitoring VBUS and VIN_3V3. These
counters ensure the supply powering the TPS65982 is stable before continuing the initialization process. The
TPS65982
SLVSD02E – MARCH 2015 – REVISED AUGUST 2021
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Product Folder Links: TPS65982
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