Xilinx Alveo U50 User Manual

Creating an MCS File and Programming the
Alveo Card
For custom RTL ow, this secon outlines the procedures to do the following:
• Create an MCS le (PROM image)
• Flash program through the maintenance connector
Create an MCS File (PROM Image)
To ensure that the PROM image is successfully loaded onto the Alveo accelerator card at power
on, the starng address must be set to 0x01002000 and the interface set to spix4 when
creang the MCS le. Details on adding this to the MCS le can be found in the UltraScale
Architecture Conguraon User Guide (UG570).
The Alveo accelerator card's Quad SPI conguraon ash memory contains a protected region,
with the factory base image at the 0x00000000 address space. This base image points to the
customer programmable region at a 0x01002000 address space oset.
In addion, the following code must be placed in the project XDC le to correctly congure the
MCS le.
# Bitstream Configuration
# ------------------------------------------------------------------------
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design]
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design]
# ------------------------------------------------------------------------
Once the XDC le has been updated, generate the MCS le using the following command (note
the quotaons are required):
write_cfgmem -force -format mcs -interface spix4 -size 1024 -loadbit "up 0x01002000
<input_le.bit>" -le "<output_le.mcs>"
Where:
• <input_le.bit> is the lename of the input .bit le
• <output_le.mcs> is the MCS output lename
Chapter 2: Vivado Design Flow
UG1371 (v1.2) December 18, 2019 www.xilinx.com
Alveo U50 Accelerator Card User Guide 12
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Xilinx Alveo U50 Specifications

General

Brand	Xilinx
Model	Alveo U50
Category	Computer Hardware
Language	English

Summary

Chapter 1: Introduction

Card Features

Lists the key features of the Alveo U50 accelerator card.

Block Diagram

Design Flows

Outlines the recommended design methodologies for targeting the Alveo U50 card.

Chapter 2: Vivado Design Flow

Board Support Files for the Alveo U50 Card

Steps to update the board support repository for Vivado development.

Creating an RTL Project Based on the U50 Board File

Guide to creating a new RTL project using the U50 board file in Vivado.

Creating an MCS File and Programming the Alveo Card

Procedures for creating an MCS file and flashing the Alveo card.

Chapter 3: Card Installation and Configuration

Standard ESD Measures

Guidelines for preventing electrostatic discharge damage during handling.

Installing Alveo Data Center Accelerator Cards in Server Chassis

Guidance on physical installation of the card into a server.

FPGA Configuration

Chapter 4: Card Component Description

UltraScale+ FPGA

Maintenance Connector Interface

PCI Express Endpoint

Card Power System

Appendix A: Xilinx Design Constraints (XDC) File