Xilinx Alveo U50 User Manual

Design Flows
The preferred opmal design ow for targeng the Alveo Data Center accelerator card uses the
Vis™ unied soware plaorm. However, tradional design ows, such as RTL or HLx are also
supported using the Vivado
®
Design Suite tools. The following gure shows a summary of the
design ows.
Figure 4: Alveo Data Center Accelerator Card Design Flows
High complexity
Slowest
High
Simplicity
Time to Market
Hardware Expertise Required
Complexity abstracted
Fastest
Low
RTL Flow HLx Flow (IP integrator)
Traditional Flows
Target Platform
Vitis
X22272-020419
Requirements for the dierent design ows are listed in the following table.
Table 2: Requirements to Get Started with Alveo Data Center Accelerator Card Design
Flows
RTL Flow HLx Flow Vitis
Flow documentation UG949
1
UG895
2
UG1416
3
Vivado tools support Board support XDC Board support XDC N/A
Programming the FPGA Vivado Hardware Manager Vivado Hardware Manager UG1370
4
Notes:
1. UltraFast Design Methodology Guide for the Vivado Design Suite (UG949).
2. Vivado Design Suite User Guide: System-Level Design Entry (UG895). See “Using the Vivado Design Suite Platform Board
Flow” in Chapter 2 and Appendix A.
3. Vitis Accelerated Flow in the Vitis Unified Software Platform Documentation (UG1416).
4. Alveo U50 Data Center Accelerator Card Installation Guide (UG1370).
Chapter 1: Introduction
UG1371 (v1.2) December 18, 2019 www.xilinx.com
Alveo U50 Accelerator Card User Guide 9
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Xilinx Alveo U50 Specifications

General

Brand	Xilinx
Model	Alveo U50
Category	Computer Hardware
Language	English