Xilinx Alveo U50 User Manual

Installing Alveo Data Center Accelerator
Cards in Server Chassis
For hardware and soware installaon procedures, see the Alveo U50 Data Center Accelerator
Card Installaon Guide (UG1370).
Because each server or PC vendor's hardware is dierent, for physical board installaon
guidance, see the manufacturer’s PCI Express
®
board installaon instrucons.
FPGA Configuration
The Alveo U50 accelerator card supports two UltraScale+™ FPGA conguraon modes:
• Quad SPI ash memory
• JTAG (through maintenance port)
The FPGA bank 0 mode pins are hardwired to M[2:0] = 001 master SPI mode with pull-up/down
resistors.
At power up, the FPGA is congured by the QSPI NOR ash device (Micron
MT25QU01GBB8E12-0SIT) with the FPGA_CCLK operang at a clock rate of up to 85 MHz
using the master serial conguraon mode.
If the JTAG cable is plugged in, QSPI conguraon might not occur. JTAG mode is always
available independent of the mode pin sengs.
For complete details on conguring the FPGA, see the UltraScale Architecture Conguraon User
Guide (UG570).
Table 3: Configuration Modes
Configuration Mode M[2:0] Bus Width CCLK Direction
Master SPI 001 x1, x2, x4 FPGA output
JTAG Not applicable – JTAG overrides x1 Not applicable
Chapter 3: Card Installation and Configuration
UG1371 (v1.2) December 18, 2019 www.xilinx.com
Alveo U50 Accelerator Card User Guide 15
Send Feedback

Xilinx Alveo U50 Specifications

General

Brand	Xilinx
Model	Alveo U50
Category	Computer Hardware
Language	English