Xilinx Alveo U50 User Manual

Revision History
The following table shows the revision history for this document.
Section Revision Summary
12/18/2019 Version 1.2
Card Features Added a note about HBM pseudo channels.
FPGA Configuration Updated the clock rate for FPGA_CCLK.
UltraScale+ FPGA Added a note about HBM pseudo channels.
Maintenance Connector Interface Added a tip about the Alveo Programming Cable.
SFP-DD Module Connectors Added a note about the supported interfaces.
Status LEDs Updated the tables and added a new table.
10/31/2019 Version 1.1
General updates. Updated to the Vitis unified software platform throughout.
Chapter 1: Introduction
• Removed HBM2 bandwidth from first paragraph.
• Updated figure.
• Updated description of card interfaces.
Card Features
• Removed bullets about HBM2 memory.
• Added note about power rails.
Board Support Files for the Alveo U50 Card Added link for Xilinx Board Store to introductory paragraph.
Card Power System
• Updated paragraph with power rail information.
• Added tip about monitoring power system telemetry.
Appendix B: Regulatory and Compliance Information Added safety, EMC, and other compliance information.
09/10/2019 Version 1.0.1
General updates. Editorial updates only. No technical content updates.
08/02/2019 Version 1.0
Initial release N/A
Revision History
UG1371 (v1.2) December 18, 2019 www.xilinx.com
Alveo U50 Accelerator Card User Guide 2
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Xilinx Alveo U50 Specifications

General

Brand	Xilinx
Model	Alveo U50
Category	Computer Hardware
Language	English