Xilinx Alveo U50 User Manual

Chapter 4
Card Component Description
This chapter provides a funconal descripon of the components of the Alveo™ U50 Data
Center accelerator card.
UltraScale+ FPGA
The Alveo U50 accelerator card is populated with the 16 nm UltraScale+™ XCU50 FPGA.
This UltraScale+ HBM device incorporates two 4 GB high-bandwidth memory (HBM) stacks
adjacent to the device die. Using SSI technology, the device communicates to the HBM stacks
through memory controllers that connect through the silicon interposer at the boom of the
device. Each XCU50 FPGA contains two 4 GB HBM stacks, resulng in up to 8 GB of HBM per
device. The device includes 32 HBM AXI interfaces used to communicate with the HBM. The
exible addressing feature that is provided by a built-in switch allows for any of the 32 HBM AXI
interfaces to access any memory address on either one or both of the HBM stacks. This exible
connecon between the device and the HBM stacks is helpful for oorplanning and ming
closure.
Note: The xilinx_u50_xdma_201920_2 plaorm allows a maximum of 30 of the 32 available HBM pseudo
channels to be used. Using more will generate errors during hardware build. Xilinx recommends using
pseudo-channels 0:29 because pseudo channels 30 and 31 need to route across fabric resources shared
with the stac region possibly resulng in lower performance.
Quad SPI Flash Memory
The Quad SPI device provides 1 Gb of nonvolale storage.
• Part number: MT25QU01GBBB8E12-0AAT (Micron)
• Supply voltage: 1.8V
• Datapath width: 4 bits
• Data rate: variable
Chapter 4: Card Component Description
UG1371 (v1.2) December 18, 2019 www.xilinx.com
Alveo U50 Accelerator Card User Guide 16
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Xilinx Alveo U50 Specifications

General

Brand	Xilinx
Model	Alveo U50
Category	Computer Hardware
Language	English